Part Number: AM6421
Tool/software:
Hello,
On our device, we are trying to use bank based interrupts with some code taken from the mcu_plus_sdk, however, we are having issues. First, I'll start out with the code we currently have:
int32_t IOLM_SOC_UTIL_gpioIrqSet(uint32_t u32BankNumber_p,
uint32_t u32IntRouter_p,
uint32_t u32IntSrcID_p,
uint32_t u32IntDstID_p,
uint32_t u32BankSrcIndexBase_p)
{
int32_t retVal = SystemP_FAILURE;
struct tisci_msg_rm_irq_set_req rmIrqReq;
struct tisci_msg_rm_irq_set_resp rmIrqResp;
/* For setting the IRQ for GPIO using sciclient APIs, we need to populate
* a structure, tisci_msg_rm_irq_set_req instantiated above. The definition
* of this struct and details regarding the struct members can be found in
* the tisci_rm_irq.h.
*/
/* Initialize all flags to zero since we'll be setting only a few */
rmIrqReq.valid_params = 0U;
/* Our request has a destination id, so enable the flag for DST ID */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
/* DST HOST IRQ is the output index of the interrupt router. We need to make sure this is also enabled as a valid
* param */
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
/* This is not a global event */
rmIrqReq.global_event = 0U;
/* Our interrupt source would be the GPIO peripheral. The source id has to be a device id recognizable by the SYSFW.
* The list of device IDs can be found in tisci_devices.h file under
* source/drivers/sciclient/include/tisci/am64x_am243x/. In GPIO case there are 3 possible options - TISCI_DEV_GPIO0,
* TISCI_DEV_GPIO1, TISCI_DEV_MCU_GPIO0. For input interrupt, we need to choose the TISCI_DEV_GPIO1
*/
rmIrqReq.src_id = u32IntSrcID_p;
/* This is the interrupt source index within the GPIO peripheral */
rmIrqReq.src_index = u32BankSrcIndexBase_p + u32BankNumber_p;
/* This is the destination of the interrupt, usually a CPU core. Here we choose the TISCI device ID for R5F0-0 core.
* For a different core, the corresponding TISCI device id has to be provided */
rmIrqReq.dst_id = u32IntDstID_p;
/* This is the output index of the interrupt router. This depends on the core and board configuration */
rmIrqReq.dst_host_irq = u32IntRouter_p;
/* Rest of the struct members are unused for GPIO interrupt */
rmIrqReq.ia_id = 0U;
rmIrqReq.vint = 0U;
rmIrqReq.vint_status_bit_index = 0U;
rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
/* To set the interrupt we now invoke the Sciclient_rmIrqSet function which
* will find out the route to configure the interrupt and request DMSC to
* grant the resource
*/
retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
return retVal;
}
This comes from mcu_plus_sdk/docs/api_guide_am64x/DRIVERS_SCICLIENT_PAGE.html.
int32_t IOLM_SOC_UTIL_registerGPIOInterrupt(HwiP_Object* gpioHwiObject_p,
uint32_t u32Bank_p,
uint32_t u32Base_p,
uint32_t u32BaseIndex_p,
uint32_t u32Router_p,
uint32_t u32Src_p,
uint32_t u32Dst_p,
HwiP_FxnCallback vISR_p)
{
int32_t retVal = SystemP_SUCCESS;
HwiP_Params hwiPrms;
// setup the GPIO input interrupt capability
// interrupt router needs to exist, ie. MCU_GPIO0 to R50_0
retVal = IOLM_SOC_UTIL_gpioIrqSet(u32Bank_p, u32Router_p, u32Src_p, u32Dst_p, u32BaseIndex_p);
if (SystemP_SUCCESS == retVal)
{
GPIO_bankIntrEnable(u32Base_p, u32Bank_p); // not pin interrupt
/* Register pin interrupt */
HwiP_Params_init(&hwiPrms);
hwiPrms.intNum = u32Router_p;
hwiPrms.callback = vISR_p;
hwiPrms.args = (void*)u32Bank_p; // NOLINT
retVal = HwiP_construct(gpioHwiObject_p, &hwiPrms);
}
else
{
printf("Error setting up interrupt.\n");
}
return retVal;
}
This code mostly comes from mcu_plus_sdk/docs/api_guide_am64x/DRIVERS_GPIO_PAGE.html.
Here's the problem: we are trying to do state interrupts. On our board, the pins we want interrupts for are GPIO0_45, GPIO0_46, GPIO0_47, and GPIO0_48. Therefore, based on the example code in the SDK, we thought these were the parameters to IOLM_SOC_UTIL_registerGPIOInterrupt:
u32Bank_p: 2 (This only covers pins GPIO0_45:47, but we got this value because there are 16 pins per bank)
u32Base_p: CSL_GPIO0_BASE (Because the pins we want interrupts on are GPIO0)
u32BaseIndex_p: 90 (This is the one we have the most questions about. Since the SDK example is using GPIO1, we don't know if this value is correct. This value adds to the bank number to fill the src_index field in the tisci_msg_rm_irq_set_req struct, but when we try 90, it does not work)
u32Router_p: CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_8
u32Src_p: TISCI_DEV_GPIO0
u32Dst_p: TISCI_DEV_R5FSS0_CORE0
Lastly, we've done a lot of experimenting on what the value of u32BaseIndex_p should be. We were successfully able to enable interrupts on one pin only by just brute forcing src_index in the tisci_msg_rm_irq_set_req struct to be equal to 45, i.e., the GPIO number of one pin we want to monitor (GPIO0_45). To us, this points towards the fact that our current code is not correctly registering bank interrupts, but rather pin interrupts.
Hopefully this is enough information, let me know if you need more. Thank you
