TDA4VL-Q1: How to configure ITAPDLYENA for DDR52

Hi Diwakar,

Diwakar Dhyani said:

Required changes are already taken care in the 6.1 kernel release, you can take a look into the patch.

When I use the sdhci_am654.c file from this commit, MMCSD0_SS_PHY_CTRL_4_REG @ 0x04F8810C value is 0x00106000, which indicates that the input delay is still not enabled.

In the emmc driver code shown below, I found that only HS200 and HS400 can tune input delay, does this mean that DDR52 does not need to enable input delay? But in the datasheet DDR52 mode needs to enable input delay. which one is right?

// board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/drivers/mmc/core/mmc.c

static int mmc_init_card(struct mmc_host *host, u32 ocr,
	struct mmc_card *oldcard)
{
    ...
	if (mmc_card_hs200(card)) {
		host->doing_init_tune = 1;

		err = mmc_hs200_tuning(card);
		if (!err)
			err = mmc_select_hs400(card);

		host->doing_init_tune = 0;

		if (err)
			goto free_card;

	} else if (!mmc_card_hs400es(card)) {
	    /* Select the desired bus width optionally */
		err = mmc_select_bus_width(card);
		if (err > 0 && mmc_card_hs(card)) {
			err = mmc_select_hs_ddr(card);
			if (err)
				goto free_card;
		}
	}
	...
}

Thanks
Regards
quanfeng

Hi quanfeng

Does this condition is not hitting?

Quanfeng Fu said:

In the emmc driver code shown below, I found that only HS200 and HS400 can tune input delay, does this mean that DDR52 does not need to enable input delay? But in the datasheet DDR52 mode needs to enable input delay. which one is right?

Tuning is only required for the HS200 and HS400 speed mode you can refer to the JEDEC v5.1 spec for the same.But we do set the value statically during the set clock function call for the other speed mode.

Regards
Diwakar

Hi Diwakar, 

Diwakar Dhyani said:

Does this condition is not hitting?

This condition is hitting, but the default itap_del_sel and itap_del_ena values are 0.

Diwakar Dhyani said:

Tuning is only required for the HS200 and HS400 speed mode you can refer to the JEDEC v5.1 spec for the same.But we do set the value statically during the set clock function call for the other speed mode.

The problem is that in DDR52 mode TDA4VL needs tuning, which is different from the JEDEC v5.1 spec. 

When I add the following code to enable tuning, the kernel reports "No passing ITAPDLY, return 0" and fails to enable tuning.

diff --git a/ti-processor-sdk-linux-j721s2-evm-08_06_01_02/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/drivers/mmc/host/sdhci.c b/ti-processor-sdk-linux-j721s2-evm-08_06_01_02/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/drivers/mmc/host/sdhci.c
index 133f0d3764..a50ab31a11 100644
--- a/ti-processor-sdk-linux-j721s2-evm-08_06_01_02/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/drivers/mmc/host/sdhci.c
+++ b/ti-processor-sdk-linux-j721s2-evm-08_06_01_02/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/drivers/mmc/host/sdhci.c
@@ -2890,6 +2890,7 @@ int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)

 	case MMC_TIMING_UHS_SDR104:
 	case MMC_TIMING_UHS_DDR50:
+	case MMC_TIMING_MMC_DDR52:
 		break;

 	case MMC_TIMING_UHS_SDR50:

diff --git a/ti-processor-sdk-linux-j721s2-evm-08_06_01_02/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/drivers/mmc/core/mmc.c b/ti-processor-sdk-linux-j721s2-evm-08_06_01_02/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/drivers/mmc/core/mmc.c
index 87807ef010..5f14411c33 100644
--- a/ti-processor-sdk-linux-j721s2-evm-08_06_01_02/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/drivers/mmc/core/mmc.c
+++ b/ti-processor-sdk-linux-j721s2-evm-08_06_01_02/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56/drivers/mmc/core/mmc.c
@@ -6,6 +6,7 @@
  *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
  *  MMCv4 support Copyright (C) 2006 Philip Langdale, All Rights Reserved.
  */
+#define DEBUG

 #include <linux/err.h>
 #include <linux/of.h>
@@ -1784,6 +1785,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
 	if (err)
 		goto free_card;

+    printk("fqf card->host->ios.timing %d 111111 \r\r ", card->host->ios.timing);
+
 	if (mmc_card_hs200(card)) {
 		host->doing_init_tune = 1;

@@ -1806,6 +1809,20 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
 		}
 	}

+    printk("fqf card->host->ios.timing %d 222222222\r\r ", card->host->ios.timing);
+
+    if (mmc_card_ddr52(card))
+    {
+        host->doing_init_tune = 1;
+
+        err = mmc_execute_tuning(card);
+
+		host->doing_init_tune = 0;
+
+		if (err)
+			goto free_card;
+    }
+
 	/*
 	 * Choose the power class with selected bus interface
 	 */

Here are the kernel logs

[    1.409528] mmc0: CQHCI version 5.10
[    1.417638] mmc1: CQHCI version 5.10
[    1.419479] sdhci-am654 4f80000.mmc: Couldn't find ti,otap-del-sel-sd-hs
[    1.423030] sdhci-am654 4fb0000.mmc: Couldn't find ti,otap-del-sel-mmc-hs
[    1.429702] sdhci-am654 4f80000.mmc: Couldn't find ti,otap-del-sel-sdr12
[    1.436512] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fca100
[    1.443152] sdhci-am654 4f80000.mmc: Couldn't find ti,otap-del-sel-sdr25
[    1.443155] sdhci-am654 4f80000.mmc: Couldn't find ti,otap-del-sel-sdr50
[    1.449674] sdhci-am654 4fb0000.mmc: Couldn't find ti,otap-del-sel-ddr52
[    1.456342] sdhci-am654 4f80000.mmc: Couldn't find ti,otap-del-sel-sdr104
[    1.456344] sdhci-am654 4f80000.mmc: Couldn't find ti,otap-del-sel-ddr50
[    1.463185] sdhci-am654 4fb0000.mmc: Couldn't find ti,otap-del-sel-hs200
[    1.469706] sdhci-am654 4f80000.mmc: Couldn't find ti,otap-del-sel-hs200
[    1.469709] sdhci-am654 4f80000.mmc: Couldn't find ti,otap-del-sel-hs400
[    1.470093] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 0 clock 0  !!!!!!!!
[    1.476549] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fca100
[    1.483196] fqf sdhci_am654_write_itapdly val 0x00100110
[    1.489877] sdhci-am654 4fb0000.mmc: Couldn't find ti,otap-del-sel-hs400
[    1.506575] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 0 clock 0  !!!!!!!!
[    1.513282] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8)
[    1.518015] fqf sdhci_am654_write_itapdly val 0x00100110
[    1.526527] ti-udma 31150000.dma-controller: Channels: 60 (tchan: 30, rchan: 30, gp-rflow: 16)
[    1.548298] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 0 clock 400000  !!!!!!!!
[    1.554765] davinci_mdio c200f00.mdio: Configuring MDIO in manual mode
[    1.560706] fqf sdhci_am654_write_itapdly val 0x00100110
[    1.575858] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
[    1.593671] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[    1.601552] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 0 clock 400000  !!!!!!!!
[    1.608964] davinci_mdio c200f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.610243] fqf sdhci_am654_write_itapdly val 0x00100110
[    1.619202] dp83812_read_straps: Strap is 0x11C0
[    1.628999] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 0 clock 400000  !!!!!!!!
[    1.637692] fqf sdhci_am654_write_itapdly val 0x00100110
[    1.639488] mmc1: new high speed SDHC card at address aaaa
[    1.651390] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 0 clock 400000  !!!!!!!!
[    1.660074] fqf sdhci_am654_write_itapdly val 0x00100110
[    1.665690] mmcblk1: mmc1:aaaa SA16G 14.8 GiB
[    1.691323] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 0 clock 400000  !!!!!!!!
[    1.700011] fqf sdhci_am654_write_itapdly val 0x00100110
[    1.705341] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 0 clock 400000  !!!!!!!!
[    1.714024] fqf sdhci_am654_write_itapdly val 0x00100110
[    1.722006] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 0 clock 400000  !!!!!!!!
[    1.730692] fqf sdhci_am654_write_itapdly val 0x00100110
[    1.751191] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 0 clock 400000  !!!!!!!!
[    1.759876] fqf sdhci_am654_write_itapdly val 0x00100110
[    1.777409] mmc0: Command Queue supported depth 16
[    1.783879] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 1 clock 400000  !!!!!!!!
[    1.792563] fqf sdhci_am654_write_itapdly val 0x0010010a
[    1.798184] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 1 clock 52000000  !!!!!!!!
[    1.807040] fqf sdhci_am654_write_itapdly val 0x0010010a
[    1.812371] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 1 clock 52000000  !!!!!!!!
[    1.821227] fqf sdhci_am654_write_itapdly val 0x0010010a
     1.826522] fqf card->host->ios.timing 1 111111
[    1.826595] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 1 clock 52000000  !!!!!!!!
[    1.840313] fqf sdhci_am654_write_itapdly val 0x0010010a
[    1.846601] sdhci-am654 4f80000.mmc: fqf sdhci_am654_set_clock timing 8 clock 52000000  !!!!!!!!
[    1.856470] fqf sdhci_am654_write_itapdly val 0x00106000
     1.861786] fqf card->host->ios.timing 8 222222222
[    1.861790] sdhci-am654 4f80000.mmc: fqf sdhci_am654_platform_execute_tuning ++++++++++++
[    1.863065] davinci_mdio c200f00.mdio: phy[0]: device c200f00.mdio:00, driver TI DP83TC813R-Q1
[    1.866835] fqf sdhci_am654_write_itapdly val 0x00106100
[    1.875140] am65-cpsw-nuss c200000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[    1.901698] fqf sdhci_am654_write_itapdly val 0x00106101
[    1.901820] am65-cpsw-nuss c200000.ethernet: Use random MAC address
[    1.913319] fqf sdhci_am654_write_itapdly val 0x00106102
[    1.913321] am65-cpsw-nuss c200000.ethernet: initialized cpsw ale version 1.4
[    1.913323] am65-cpsw-nuss c200000.ethernet: ALE Table size 64
[    1.931611] fqf sdhci_am654_write_itapdly val 0x00106103
[    1.933061] am65-cpsw-nuss c200000.ethernet: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0
[    1.945859] fqf sdhci_am654_write_itapdly val 0x00106104
[    1.951060]  mmcblk1: p1 p2 p3 p4 < p5 p6 p7 p8 p9 p10 >
[    1.956538] fqf sdhci_am654_write_itapdly val 0x00106105
[    1.960453] am65-cpsw-nuss c200000.ethernet: set new flow-id-base 82
[    1.968285] fqf sdhci_am654_write_itapdly val 0x00106106
[    1.973137] debugfs: Directory 'pd:39' with parent 'pm_genpd' already present!
[    1.980879] fqf sdhci_am654_write_itapdly val 0x00106107
[    1.980949] debugfs: Directory 'pd:38' with parent 'pm_genpd' already present!
[    1.993465] fqf sdhci_am654_write_itapdly val 0x00106108
[    1.994041] debugfs: Directory 'pd:276' with parent 'pm_genpd' already present!
[    2.006146] fqf sdhci_am654_write_itapdly val 0x00106109
[    2.006743] debugfs: Directory 'pd:154' with parent 'pm_genpd' already present!
[    2.018822] fqf sdhci_am654_write_itapdly val 0x0010610a
[    2.024236] fqf sdhci_am654_write_itapdly val 0x0010610b
[    2.029617] fqf sdhci_am654_write_itapdly val 0x0010610c
[    2.034989] fqf sdhci_am654_write_itapdly val 0x0010610d
[    2.040376] fqf sdhci_am654_write_itapdly val 0x0010610e
[    2.041422] ALSA device list:
[    2.048690]   No soundcards found.
[    2.048696] fqf sdhci_am654_write_itapdly val 0x0010610f
[    2.057462] fqf sdhci_am654_write_itapdly val 0x00106110
[    2.062864] fqf sdhci_am654_write_itapdly val 0x00106111
[    2.068249] fqf sdhci_am654_write_itapdly val 0x00106112
[    2.073626] fqf sdhci_am654_write_itapdly val 0x00106113
[    2.079019] fqf sdhci_am654_write_itapdly val 0x00106114
[    2.084429] fqf sdhci_am654_write_itapdly val 0x00106115
[    2.089807] fqf sdhci_am654_write_itapdly val 0x00106116
[    2.095182] fqf sdhci_am654_write_itapdly val 0x00106117
[    2.100559] fqf sdhci_am654_write_itapdly val 0x00106118
[    2.105954] fqf sdhci_am654_write_itapdly val 0x00106119
[    2.111375] fqf sdhci_am654_write_itapdly val 0x0010611a
[    2.116756] fqf sdhci_am654_write_itapdly val 0x0010611b
[    2.122128] fqf sdhci_am654_write_itapdly val 0x0010611c
[    2.127501] fqf sdhci_am654_write_itapdly val 0x0010611d
[    2.132874] fqf sdhci_am654_write_itapdly val 0x0010611e
[    2.138246] fqf sdhci_am654_write_itapdly val 0x0010611f
[    2.143617] sdhci-am654 4f80000.mmc: No passing ITAPDLY, return 0
[    2.149705] fqf sdhci_am654_write_itapdly val 0x00106100
[    2.155265] mmc0: Command Queue Engine enabled
[    2.159709] mmc0: new DDR MMC card at address 0001

Thanks
Regards
quanfeng

HI quanfeng

HI quanfeng,

You are getting 0 as you haven't added ti,itap-del-sel-ddr52 property under the emmc node.

Quanfeng Fu said:

The problem is that in DDR52 mode TDA4VL needs tuning, which is different from the JEDEC v5.1 spec. 

When I add the following code to enable tuning, the kernel reports "No passing ITAPDLY, return 0" and fails to enable tuning.

This is not correct, the tuning is not required for DDR52 mode, the value mentioned in the data manual is static and that can be configured using device tree by adding the property.

No need to perform a tuning operation in the driver for the DDR52.

Regards
Diwakar

Hi Diwakar, 

What is the value of the ti,itap-del-sel-ddr52 property of TDA4VL, I don't see a corresponding value in the datasheet.

Thanks
Regards
quanfeng

Hi quanfeng 

This seems incorrect in the data sheet 

ii am checking internally for the correct value, one more thing is that this is required to adjust the sampling clock are you seeing any issue with the DDR speed mode ?

Regards
Diwakar

Hi Diwakar,

Diwakar Dhyani said:

i am checking internally for the correct value

Did you get any results?

Diwakar Dhyani said:

one more thing is that this is required to adjust the sampling clock are you seeing any issue with the DDR speed mode ?

In DDR speed mode, the eMMC clock is a normal 50Mhz.

Thanks
Regards
quanfeng

Hi quanfeng

If you are not facing any issue with the read/write , it is okay if you are not keeping the itap delay value for the DDR52.

Regards
Diwakar