• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 214 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

uPP enable

whitsydaddy
Prodigy 190 points


Hello,

 

I have 2 questions about the enable bit for the uPP.  I am looking to pass data between a FPGA and OMAP L138 on the Critical Link mityDSP board. I am writing my own linux kernel module to run on the ARM in the OMAP.

Question 1:     I am looking at the timing diagrams in the uPP peripheral documentation (pages 18-19 SPRUGJ5B).  The documentation states that enable is driven for every valid data       word,  For the default polarity it will go high and once a word is transmitted low until the next word?

Question 2:  Also, in the diagrams (figure 9 and 10) it looks like enable goes high for 3 words then low until the next 3 words.  Am I reading this correctly?

 

thanks in advance, Scott

  • 0
    TI__Expert 8890 points

    Scott,

    The timing diagrams in the user guide show somewhat arbitrary behavior on the part of the uPP transmitter.  During a normal uPP transaction, the transmitter will assert WAIT and will not release it until the entire transfer is complete.  The transmitter will assert the START signal only on the first data word of each DMA line in the transfer.  (For a one-line transfer, the START signal will only be asserted for one data word per transfer.)

    Hope this helps.  Please let me know if this doesn't answer your questions.