Tool/software:
Hello Experts,
According to section 6.4 in the SoC datasheet, all power balls must be supplied with the voltages specified in Section 7.5, Recommended Operating Conditions, unless otherwise specified.
Also according to note11 under Table 7-6 of Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. G), rails not listed in this table are not simulated by TI due to low load transients. For more information, see the device-specific EVM layout for example implementation of these rails.
I would like to confirm if it is okay to just tie the unused power group to its voltage without any bypass capacitors to save board space and BOM cost.
For example, if OSPI is not used, can I just tie VDDSHV1 to 1V8 without placing any capacitor near the balls?
Thank you,
George
