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TMDXEVM6678L locked-out code download problem after changing DIP-Switch settings

Peter Lord
Prodigy 60 points

Hi All,

I want to transfer data from a host PC to the EVM via PCIe, and have been using two settings during my investigations; the factory-original positions, and the positions given in the readme.pdf file for the PCIE Boot Example given in .\mcsdk_2_00_02_14\tools\boot_loader\examples\pcie\docs. The PCIe boot example settings are:

SW3                SW4              SW5               SW6               SW9
(pin1, 2, 3, 4)    (pin1, 2, 3, 4)  (pin1, 2, 3, 4)   (pin1, 2, 3, 4)   (pin1)
(off, on, on, off) (on, on, on, on) (on, on, on, off) (off, on, on, on) (on)

I want to be able to download code to the EVM via the built-in USB/JTAG interface when the EVM is set-up for PCIe boot. I have tried several TMDXEVM6678L and they all exhibit the following problem:

1. With a factory-new EVM (all DIP-SW at default) I can build and download projects readily.
2. After changing the DIP switches to the PCIe configuration, CCS gives a data load error when attempting to download code:
   "Load Program Error.
    File:
    etc\etc\..\pcieboot_helloworld_evm6678l.out: a data verification error occurred, file load failed"
3. Power-cycling the EVM (and disconnecting USB) then putting the DIP switches back to factory-default the data load error remains.
4. Moving the EVM (DIP-SW factory-default) to a different PC host the new host is able to download code with no errors (default DIP-SW).
5. Reverting to the previous PC-host once again I get download errors.
6. Putting the original PC-host to sleep for the night and powering-down the EVM (and disconnecting USB cable) then re-trying the next morning I am able  to download successfully once again (but DIP-SWs are not in the setting required for PCIe).

Basically, it looks as though CCS or perhaps an underlying driver is getting itself into confused state (although it could also be some issue with the EVM).

Shutting-down CCS (Version: N201105110900) and power-cycling the PC host make no difference to this behaviour.

Questions:
* Am I right in believing that the JTAG interface should continue to work with these changed DIP-SW settings?
* What can I do to bring sanity back to the debug environment when the failed downloads occur (we have 2 other EVMs/hosts that are locked-out in this way) ?
* I've put the EVM configuration setting back to factory and power-cycled, what else should be necessary?

Thanks in anticipation.

Peter L.

  • 0
    TI__Intellectual 2180 points

    The JTAG interface itself should always work.  It looks like it is working (since you can connect), but some part of the memory map on the device is not working as you expect.

    You probably updated the IBL as part of the readme.pdf in the pcie boot example.  This is the bootloader which executes any time the switches are in any position other no boot mode.  This is true whether the switches are in default settings or pcie boot settings.

    First, if you set switch 3 to off/on/on/on, it is set to no boot mode.  In this case the IBL doesn't run, and therefore the initial state of the board will be the same.  You don't have to adjust the other switches because they are ignored in no boot mode.

    Next, if you execute the "system reset" from CCS (its on the run menu), it should always work regardless of the switches.  The IBL doesn't have a chance to run when you do the system reset with first core in the suspended state.

    Since the IBL takes some time to execute, you can get different behavior if you try to connect immediately after reset button or power cycle vs waiting a few seconds.  This could explain the differences in behavior you are seeing between different PCs and power cycle of the PC.

    I also assume that you loaded the GEL file per the instructions in the EVM's getting started guide (C:\Program Files\Texas Instruments\ccsv5\ccs_base_5.0.3.00028\emulation\boards\evmc6678l\gel\evmc6678l.gel).  When you are in no boot mode, this gel will automatically power on all the peripherals and configure the DDR.  When you are not in no-boot mode (such as default or pcie), the GEL does not configure the peripherals and DDR (if the DDR is not configured then you can't load program/data into DDR which will always result in a load failure).  However, if you perform system reset, followed by executing the Global_Default_setup() under the scripts menu, it should behave the same way regardless of switch settings, IBL, wait times, reboots, etc.

    Does this help make the EVM predictable each time you try to reload?  If not, which address is CCS complaining about when the load fails?

  • 0 in reply to John Dowdal
    Prodigy 60 points

    Thanks John, that helped tremendously.