Hello,
here is my setup:
C6748 DSP
using a McBSP that is initialized using the below routine. the McBSP is talking to an 320AIC20k codec. the frame sync is set to 8kHz, the codec is the master of the clocks.
I'm sure i need to tell you more but i can't think of anything overly important.
the problem is that the McBSP transmit interrupt (which happens on every XRDY) will stop posting. this used to only happen on the emulator but now it happens off the emulator, and right now it is a very serious problem with our latest boards (our own custom boards). on the emulator the XSYNCERROR bit was set. when HWI were disabled and re-enabled the interrupt would fire once but the sync error would return. we also tried resetting the McBSP after the FS when the syncerror was detected but that just resulted in resetting the McBSP on EVERY frame sync.
i had a theory for why it didn't work. in our initialization code the McBSP and the codec were initialized right away and then the DSP would go off and do some other things before leaving main and turning on interrupts (possibly as long as 3 seconds). i theorized that the McBSP saw too many frame syncs before HWI were enabled and that messed it up. when i moved the initialization of the McBSP and Codec to the end of main just before HWI were enabled it seemed to fix the problem, but on the latest boards we got it only fixes it for a short time before we get stuck with no more mcBSP Tx interrupts.
based on the codec we are using and the McBSP settings we have is there anything anybody can see that could cause something like this to happen? any help would be appreciated.
void init_McBSP(void)
{
U32 AntiLockupCounter;
MCBSP1_SPCR = 0x00000000; /* Reset the McBSP before writing control regs */
MCBSP1_RCR = 0x00010140; /* Receive control Reg
RPHASE = 0 Single Phase Frame
RFRLEN2 = 0000000 1 Word in Phase 2
RWDLEN2 = 000 8 bit Word in Phase 2
RCOMPAND = 00 No companding
RFIG = 0 Restart transfer if extra FS detected
RDATDLY = 01 1 bit data delay
reserved = 0 Reserved location
RFRLEN1 = 0000001 2 Words in Phase 1
RWDLEN1 = 010 16 bit Word in Phase 1
RWDREVRS = 0 Disable 32 bit reversal
reserved = 0000 Reserved locations */
MCBSP1_XCR = 0x00010140; /* Transmit control Reg
XPHASE = 0 Single Phase Frame
XFRLEN2 = 0000000 1 Word in Phase 2
XWDLEN2 = 000 8 bit Word in Phase 2
XCOMPAND = 00 No companding
XFIG = 0 Restart transfer if extra FS detected ***
XDATDLY = 01 1 bit data delay
reserved = 0 Reserved location
XFRLEN1 = 0000001 2 Words in Phase 1
XWDLEN1 = 010 16 bit Word in Phase 1
XWDREVRS = 0 Disable 32 bit reversal
reserved = 0000 Reserved locations */
MCBSP1_MCR = 0x00000000; /* Multi-Channel control Reg
* reserved = 000000 Reserved locations
* XMCME = 0 2 partition mode. A & B used only
* XPBBLK = 00 Use Tx B Block 1, channels 16-31
* XPABLK = 00 Use Tx A Block 0, channels 0-15
* XCBLK = 000 Current Tx block used: Block 0 channels 0-15
* XMCM = 00 Disable all transmit multi-channels
* reserved = 000000 Reserved locations
* RMCME = 0 2 partition mode. A & B used only
* RPBBLK = 00 Use Rx B Block 1, channels 16-31
* RPABLK = 00 Use Rx A Block 0, channels 0-15
* RCBLK = 000 Current Rx block used: Block 0 channels 0-15
* reserved = 0 Reserved locations
* RMCM = 0 Disable all recieve multi-channels */
MCBSP1_PCR = 0x00000000; /* Pin control Reg
reserved = 00000000000000000000
FSXM = 0 XMIT Frame Sync from external source
FSRM = 0 RECV Frame Sync from external source
CLKXM = 0 CLKX is input, external clock
CLKRM = 0 CLKR is input, external clock
SCLKME = 0 signal is on CLKS pin
reserved = 00 Reserved locations
FSXP = 0 Tx FS pulse active high
FSRP = 0 Rx PS pulse active high
CLKXP = 0 Tx data sampled on rising edge of CLKX
CLKRP = 0 Rx data sampled on falling edge of CLKR */
MCBSP1_SPCR = 0x02002000; /* Serial port control Reg
reserved = 000000 Reserved locations
FREE = 1 On emulation halt serial clock continues
SOFT = 0 Free = 1, so value makes no difference
FRST = 0 frame sync generator reset
GRST = 0 sample rate generator reset
XINTM = 00 XINT generated by XRDY=1
XSYNCERR = 0 no frame sync error detected
XEMPTY = 0 XSR is empty
XRDY = 0 transmitter is not ready
XRST = 0 Transmitter is disabled and in reset
DLB = 0 digital loopback disabled
RJUST = 01 right justify and sign extend
CLKSTP = 00 clock stop mode is disabled
reserved = 000 Reserved locations
DXENA = 0 DX enabler is off
reserved = 0 Reserved locations
RINTM = 00 RINT generated by RRDY=1
RSYNCERR = 0 no synchronization error detected
RFULL = 0 RBR is not overrun
RRDY = 0 receiver is not ready
RRST = 0 Receiver is disabled and in reset */
MCBSP1_DXR_16BIT = 0; /* Load silence into the TX register. */
/* We need to make sure the McBSP saw at least 2 SCLK cycles while its held in RESET. In addition, there is a glitch in the
hardware after it is enabled for the 1st time after a C6748 RESET. We need to enable the XMIT side, wait a few SCLK's,
and then disable again. */
waitusec(20);
MCBSP1_SPCR = MCBSP1_SPCR | MCBSP_SPCR_XRST; /* Enable XMIT side of McBSP */
waitusec(20);
MCBSP1_SPCR = MCBSP1_SPCR & (~MCBSP_SPCR_XRST); /* Disable XMIT side of McBSP */
AntiLockupCounter = 0;
while( ((GPIO_IN_DATA8 & FS_INT) == 0) && (AntiLockupCounter < 500) )
{
/* Wait here until we detect the FS pin go HIGH. Users guide says to only enable the McBSP after a FS. Abort if we are
waiting for more than 1mS. If we abort, the HW is most likely screwed. */
waitusec(2);
AntiLockupCounter++;
}
waitusec(20);
MCBSP1_SPCR = MCBSP1_SPCR | (MCBSP_SPCR_XRST | MCBSP_SPCR_RRST);
