Immediately after triggering the initialization of EMIF4[0], our board is going into some kind of fault state where JTAG no longer works. These are my relevant modifications to the v2 GEL file:
/* * DDR3 EMIF Paramters set for 796.5 MHz Clock Frequency */ #define EMIF_TIM1_DDR3_796 0x1779C9FE #define EMIF_TIM2_DDR3_796 0x50608074 #define EMIF_TIM3_DDR3_796 0x009F857F #define EMIF_SDREF_DDR3_796 0x10001841 //#define EMIF_SDCFG_DDR3_796 0x62A73832 /* 32 bit ddr3, CL=11, 8 banks, CWL=8 10 bit column, 2 CS, */ #define EMIF_SDCFG_DDR3_796 (\ 0x03 << 29 | /* MEMTYPE */ \ 0x01 << 27 | /* IBANKPOS (0-ignore rsize, 1-3h-use rsize)*/ \ 0x02 << 24 | /* DDRTERM */ \ 0x01 << 5 | /* DDQS */ \ 0x01 << 21 | /* DYNODT */ \ 0x00 << 0 | /* DLL */ \ 0x01 << 18 | /* DRIVE */ \ 0x03 << 16 | /* CWL */ \ 0x00 << 14 | /* NM (1=16bit,0=32bit)*/ \ 0x0E << 10 | /* CL */ \ 0x06 << 7 | /* RSIZE */ \ 0x03 << 4 | /* IBANK */ \ 0x00 << 3 | /* EBANK */ \ 0x02 << 0 /* PAGESIZE */ \ ) #define EMIF_PHYCFG_DDR3_796 0x00000110 /* local odt = 1, read latency = 11 (max = 12, min=6) */
EMIF4P_Init(unsigned int TIM1, unsigned int TIM2, unsigned int TIM3, unsigned int SDREF, unsigned int SDCFG, unsigned int RL){
GEL_TextOut("\tSetup EMIF0 CFG ..... \n","Output",1,1,1);
/*Program EMIF0 CFG Registers*/
WR_MEM_32(EMIF4_0_SDRAM_TIM_1, TIM1);
WR_MEM_32(EMIF4_0_SDRAM_TIM_1_SHADOW, TIM1);
WR_MEM_32(EMIF4_0_SDRAM_TIM_2, TIM2);
WR_MEM_32(EMIF4_0_SDRAM_TIM_2_SHADOW, TIM2);
WR_MEM_32(EMIF4_0_SDRAM_TIM_3, TIM3);
WR_MEM_32(EMIF4_0_SDRAM_TIM_3_SHADOW, TIM3);
GEL_TextOut("\tSetting EMIF4_0_SDRAM_CONFIG to %x\n", "Output",1,1,1,SDCFG);
WR_MEM_32(EMIF4_0_SDRAM_CONFIG, SDCFG);
/* WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, SDREF); */
/* WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL_SHADOW, SDREF); */
WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1, RL);
WR_MEM_32(EMIF4_0_DDR_PHY_CTRL_1_SHADOW, RL);
if(TWO_EMIF){
GEL_TextOut("\tSetup EMIF1 CFG ..... \n","Output",1,1,1);
/*Program EMIF1 CFG Registers*/
WR_MEM_32(EMIF4_1_SDRAM_TIM_1, TIM1);
WR_MEM_32(EMIF4_1_SDRAM_TIM_1_SHADOW, TIM1);
WR_MEM_32(EMIF4_1_SDRAM_TIM_2, TIM2);
WR_MEM_32(EMIF4_1_SDRAM_TIM_2_SHADOW, TIM2);
WR_MEM_32(EMIF4_1_SDRAM_TIM_3, TIM3);
WR_MEM_32(EMIF4_1_SDRAM_TIM_3_SHADOW, TIM3);
WR_MEM_32(EMIF4_1_SDRAM_CONFIG, SDCFG);
/* WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, SDREF); */
/* WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL_SHADOW, SDREF); */
WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1, RL);
WR_MEM_32(EMIF4_1_DDR_PHY_CTRL_1_SHADOW, RL);
}
if(DDR2) {
/* setup a small refresh period */
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x0000613B); /* initially a large refresh period */
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x1000613B); /* trigger initialization */
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, (0x10000000|SDREF)); /* move to a smaller more correct one */
if(TWO_EMIF){
/* setup a small refresh period */
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, 0x0000613B); /* initially a large refresh period */
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, 0x1000613B); /* trigger initialization */
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, (0x10000000|SDREF)); /* move to a smaller more correct one */
}
}
if(DDR3 && 1) {
GEL_TextOut("\tInitializing EMIF0 ..... \n","Output",1,1,1);
/* setup a small refresh period */
GEL_TextOut("\tSet large refresh period..... \n","Output",1,1,1);
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x0000613B); /* initially a large refresh period */
if (RD_MEM_32(EMIF4_0_SDRAM_REF_CTRL) != 0x0000613B) {
GEL_TextOut("\tWasn't able to set large refresh period..... \n","Output",1,1,1);
}
GEL_TextOut("\tTrigger initialization..... \n","Output",1,1,1);
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, 0x1000613B); /* trigger initialization */
GEL_TextOut("\tChecking to see if it worked..... \n","Output",1,1,1);
if (RD_MEM_32(EMIF4_0_SDRAM_REF_CTRL) != 0x1000613B) {
GEL_TextOut("\tInit failed..... \n","Output",1,1,1);
}
GEL_TextOut("\tMove to smaller correct one..... \n","Output",1,1,1);
WR_MEM_32(EMIF4_0_SDRAM_REF_CTRL, (0x10000000|SDREF)); /* move to a smaller more correct one */
if(TWO_EMIF){
GEL_TextOut("\tInitializing EMIF1 ..... \n","Output",1,1,1);
/* setup a small refresh period */
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, 0x0000613B); /* initially a large refresh period */
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, 0x1000613B); /* trigger initialization */
WR_MEM_32(EMIF4_1_SDRAM_REF_CTRL, (0x10000000|SDREF)); /* move to a smaller more correct one */
}
}
if (SWLEVELINNG) {
ddr3_sw_levelling(0);
GEL_TextOut("DDR3 SWLEVELING DONE FOR EMIF0 \n","Output",1,1,1);
ddr3_sw_levelling(1);
GEL_TextOut("DDR3 SWLEVELING DONE FOR EMIF1 \n","Output",1,1,1);
}
}
What does this error mean? Should I be adjusting the TIM[1:3] registers as well as CFG?
