AM6442: Number of FSI data lane

Hi Koishiro,  FSI could use up to two RX and two TX lanes. But, could you please shrare with me from where you got this information?

thank you,

Paula

Hi Paula,

The customer just refer to datasheet.

Paula Carrillo said:

FSI could use up to two RX and two TX lanes.

Do you means only two RX lanes can be used even we have 6 of them (RX0 to RX5)?

Thanks and regards,
Koichiro Tashiro

Hi Tashiro, now I understand better your question.

AM64x has 6 x FSI RX cores and 2 x FSI TX cores.

Each  FSI RX core has: 2 RX lanes (RX_D0, RX_D1), and RX CLK

Each FSI TX core has: 2 TX lanes (TX_D0, TX_D1), and TX CLK.

Few more details of FSI signals and connections for one RX and TX core here: [FAQ] MCU-PLUS-SDK-AM243X: How-to test FSI external 1-device loopback on AM243x LP or EVM - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

thank you,

Paula

Hi Paula,

Thanks for the info.
According to the usecase described in the FAQ, TX lanes and RX lanes are the same number (1 to 1 connection).
The customer wonders why AM64x has more RX cores and asks any specific usecase where RX needs more lanes.

Thanks and regards,
Koichiro Tashiro 

Hi Pekka,

Thanks for your reply.
I understood these topologies..

Thanks and regards,
Koichiro Tashiro