Tool/software:
Hi,
My application is with heterogeneous multicore system (AM5728), and now I need to copy the data from buffer(DDR) or from L2SRAM, to 0x40500000(OCMC_RAM2). The ultimate purpose is to dump out from ARM side.
I made a 1024bytes as one block, the front 1020 bytes of data is engineering data, the last 4 bytes is CRC32 value, to make sure the data integrity. As I did test and found even data transfer to ARM and to PC, I checked the CRC32 of the block is matched with data.
But not all of the data is I expected, e.g. I have an index number by add one every cycle. I found the index is not consistent increasing.
So I thought the data as I read out and calculate CRC in DSP side is not what I'm written. Not always, but 1/5 is wrong. You can check my code below.
Question is how to make sure the data consistant and ganrantee the data is written and read correct. For L2SRAM and for data in DDR.
unsigned char DSP_PARA_DATA[DSP_PARA_DATA_LEN_IN_INT32];
#pragma DATA_SECTION(DSP_PARA_DATA, "L2SRAM")
volatile unsigned int counter_in_L2SRAM;
#pragma DATA_SECTION(counter_in_L2SRAM, "L2SRAM")
for(i = 0; i < uploadParameterLength; i+=4)
{
*(unsigned int*)(DSP_PARA_DATA+i) = (i >> 2) * 0x00000101+ 0x12340000;
}
*(uint32_t*)(DSP_PARA_DATA) = 0xDEADBEEF;
*(uint32_t*)(DSP_PARA_DATA + 4) = counter_in_L2SRAM;//transCost;
*(uint32_t*)(DSP_PARA_DATA + 8) = counter_in_L2SRAM;//count_test6;
Cache_wbInv(DSP_PARA_DATA, 1024, Cache_Type_L2, TRUE);
*(uint32_t*)(DSP_PARA_DATA + 1020) =
xcrc32((const unsigned char *)(DSP_PARA_DATA), 1020, 0);
Cache_wbInv(DSP_PARA_DATA, 1024, Cache_Type_L2, TRUE);
edma3_copy(DSP_PARA_DATA, current_block_ptr->payload + current_fill_offset, uploadParameterLength);
