AM6442: Why does calling __MRC(15,0, 9, 13, 0) crash the processor, and is there another way to get cycle count on R5F?

Greetings Andrew,

Are you initializing/configuring the PMU (Performance Monitoring Unit) before using that instruction, and if so can you share that? In addition, what mode are you operating the CPU in? This should all be contained to the individual R5 core, so it depends on two things to my understanding:

1) Operating mode (USER, SYS, ABORT, etc.): User mode is the only non-privileged mode and does not have default access to the PMU. If you're getting an abort, this could be the cause. (https://developer.arm.com/documentation/ddi0460/d/Programmers-Model/Modes-of-operation-and-execution/Modes-of-operation) 

2) PMU configuration: The PMU has to be configured and enabled. For example, in the User Enable Register of the PMU (https://developer.arm.com/documentation/ddi0460/d/Events-and-Performance-Monitor/Performance-monitoring-registers/c9--User-Enable-Register), there is a bit to set to enable access from user mode. This has to be done from a privileged mode, so could be done when the core boots.

There are other registers to enable the counters and configure the cycle counting ratio as well. For reference, here are some documentation links from ARM about the PMU and the registers available for configuration. 

https://developer.arm.com/documentation/ddi0460/d/Events-and-Performance-Monitor/About-the-PMU

https://developer.arm.com/documentation/ddi0460/d/Events-and-Performance-Monitor/Performance-monitoring-registers

Sincerely,

Lucas

Thank you for the references.  I will look at them.

In my case I was trying the __MRC instruction right after doing a processor reset.

The steps I was taking were as follows...

1)  Power on the board with blank flash memories.

2)  Start a debug session that runs..

     a) ..\..\emulation\gel\AM64x\CPU_reset.gel on the R5F_0_0 core

     b)  "..\..\emulation\gel\AM64x\AM64x.gel" on the DMSC core

3)  Use the scripting console to load SYSFW into the DMSC.

      LoadJSFile C:\ti\mcu_plus_sdk_am64x_08_05_00_24\tools\ccs_load\am64x\load_dmsc.js

4)  After that run the __MRC instruction from main() with no other init.

The CPU should have still been in whatever mode it was in right after a reset and SYSFW load.  I didn't really check the mode, since I assumed that it would be in privileged mode after reset.

On other CPUs I have tried this on the default settings seemed to allow me to read the cycle counter without extra configuration.  I will look into whether the PMU settings were this issue.