DSK6455 and McBSP integer frecuency

All of the dividers you mention are integer dividers. There is no "rounding" that occurs anywhere.

I suspect there is a typo in the datasheet example text, and that it should read

sprs276 correction said:

the PLL output PLLOUT is set to 1200 MHz and SYSCLK2 and SYSCLK3 run at 400 MHz and 200 MHz, respectively.

Since 1200 MHz is the max speed available for the device and since the dividers divide cleanly at 1200, I believe this is the right correction, rather changing the SYSCLK2 and SYSCLK3 frequencies to lower numbers.

Whatever the PLLOUT frequency is, SYSCLK2 will be SYSREFCLK/3 and SYSCLK3 will be SYSREFCLK/6.

Regards,
RandyP

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Hello RandyP

Well, if there is a typo, there are more typos: sprs276 explains that crystal clock is 50 MHz and PLLM is 20, and 50 x 20 is 1000 MHz, perhaps must say 40 MHz x 30 = 1200 MHz.

But my doubt is: DSK6455 board works with 1000 MHz, if SYSCLK3 = SYSREFCLK/6, what will be the output frecuency? 166 MHz or 166,666,666 Hz?

Please, where is "Verify answer"?

Best regards.

Manuel Fernández Ros

SYSCLK3 = SYSREFCLK/6

For SYSREFCLK = 1000 MHz, then yes, SYSCLK3 = 166.67 MHz.

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Manuel Fernández Ros,

Since the SYSREFCLK=1000MHz means the clock period = 1ns, the SYSCLK3 period = 6ns. The timer dividers will also be integer dividers, so you can generate any period that is a multiple of 6ns.

This means you cannot hit 1us exactly, or 1ms exactly. But you can choose a timer period that is whatever multiple of 6ns you wish, including .6ms or 1.2ms, for examples.

You can also choose a different input frequency on CLKIN1, a /2 or /3 predivider before PLL1, and any of the available PLLM integer multipliers. This could be done to generate a different result for SYSCLK3, but of course it would also change the SYSREFCLK frequency. These are system tradeoffs that you can make.

A good method would be to use a 1200MHz device and run SYSREFCLK at 1200MHz so the SYSCLK3 frequency can give you the timer frequency that you want.

In some of our newer devices, there is more flexibility on some of the PLLs and internal clock dividers, but for the C6455 these are the choices you can make.

Please do mark one or more of the posts with Verify Answer once you have the complete answer to your question. This will mark it so that future readers will know the thread has an answer, which post(s) offer that answer, and also let the many TI applications people know that this thread has been completed.

Regards,
RandyP

Hello RandyP and Brad,

I disagree your response. I've measure (with a frequencymeter) on CLKR pin (5-6K interface) with CLKGDV = 7 (SRGR register), then Fclkr = Fin / (7 +1) , the measure is 25 MHz. The explaining is that Fcpu / 6  = 200 MHz when Fcpu = 1000 MHz.

If I haven't made any mistake there aren't any typos on TMS320C6455 datasheet.

I think you must review your data about the dividers of PLL1.

If you think I am wrong I'd like you explain it better.

Regards.