PROCESSOR-SDK-AM64X: ospi dma write 256KB problem. need help.

Jun Tu

Expert 1680 points

Part Number: PROCESSOR-SDK-AM64X
Other Parts Discussed in Thread: TMDS64EVM, UNIFLASH

Tool/software:

Hi,

I am running the demo board. TMDS64EVM , So flash should be S28HS512T.

I am config flash to uniflash. All sector size are 256 KB, and there are 128 sectors.

I am able to config udma dac wrtie to flash.

I want to write 256KB at a time.

However, Each time I can write only 1024 bytes.

Here is my code.

App_OspiFlashDmaTrpdInit(appObj->udmaChHandle_channel1,

&udgOspiFlashDmaTrpdMemChannel1[0],

&gOspiFlashDmaTxBuf[0],

(void *)flashDstAddr1,

APP_OSPI_FLASH_DMA_TEST_SIZE_BYTES);

if I replace flashDstAddr1 by msram eg: 0x70100000, The code will be fine, without any problem.

flashDstAddr1 is from 0x80000000.

1. So what is the error? My dmss config must be right? It is probably my flash config, eg: auto polling.

by the way, I am able to read 256kbytes from flash. I am not able to write 256kbytes.

2. Also direct write was not working fine even, I write 256 bytes each time. my page size is 256 bytes.. (Direct read, indac read and indac write, works perfect.)

Thanks.

Here is my detail configuration of flash.

/* FLASH Attrs */

Flash_Attrs gFlashAttrs_S28HS512T =

{

.flashName = "S28HS512T",

.deviceId = 0x5B1A,

.manufacturerId = 0x34,

.flashSize = 67108864,

.blockCount = 256,

.blockSize = 262144,

.pageCount = 1024,

.pageSize = 256,

.sectorCount = 256,

.sectorSize = 262144,

};

/* FLASH DevConfig */

Flash_DevConfig gFlashDevCfg_S28HS512T =

{

.cmdExtType = OSPI_CMD_EXT_TYPE_REPEAT,

.enable4BAddr = TRUE,

.addrByteSupport = 1,

.fourByteAddrEnSeq = 0xA0,

.cmdWren = 0x06,

.cmdRdsr = 0x05,

.srWip = (1 << 0),

.srWel = (1 << 1),

.xspiWipRdCmd = 0x65,

.xspiWipReg = 0x00800000,

.xspiWipBit = (1 << 0),

.resetType = 0x10,

.eraseCfg = {

.blockSize = 262144,

.sectorSize = 4096,

.cmdBlockErase3B = 0xDC,

.cmdBlockErase4B = 0xDC,

.cmdSectorErase3B = 0x21,

.cmdSectorErase4B = 0x21,

.cmdChipErase = 0xC7,

.idCfg = {

.cmd = 0x9F, /* Constant */

.numBytes = 3,

.dummy4 = 0,

.dummy8 = 4,

.addrSize = 4

.protocolCfg = {

.protocol = FLASH_CFG_PROTO_8D_8D_8D,

.isDtr = TRUE,

.cmdRd = 0xEE,

.cmdWr = 0x12,

.modeClksCmd = 0,

.modeClksRd = 0,

.dummyClksCmd = 4,

.dummyClksRd = 25,

.enableType = 0,

.enableSeq = 0x00,

.protoCfg = {

.isAddrReg = TRUE,

.cmdRegRd = 0x65,

.cmdRegWr = 0x71,

.cfgReg = 0x00800006,

.shift = 0,

.mask = 0x01,

.cfgRegBitP = 1,

.strDtrCfg = {

.isAddrReg = TRUE,

.cmdRegRd = 0x65,

.cmdRegWr = 0x71,

.cfgReg = 0x00800006,

.shift = 1,

.mask = 0x02,

.cfgRegBitP = 1,

.dummyCfg = {

.isAddrReg = TRUE,

.cmdRegRd = 0x65,

.cmdRegWr = 0x71,

.cfgReg = 0x00800003,

.shift = 0,

.mask = 0x0F,

.cfgRegBitP = 11,

.flashWriteTimeout = 512,

.flashBusyTimeout = 256000000,

};

I use

Flash_open

all other code is based on the ospi_flash_dma example .

Thanks

over 1 year ago

0 Jun Tu over 1 year ago

Expert 1680 points

MPU config should be not an issue. since indirect write to flash location 0x60800000 is perfect.

0 Prashant Shivhare over 1 year ago in reply to Jun Tu

TI__Guru* 77721 points

Hi Jun,

The query has been assigned to the subject matter expert. Please allow a day or two for the expert to get back to you.

Thanks for your patience!!

0 Vaibhav Kumar over 1 year ago

TI__Guru 53553 points

Greetings Jun,

Thank you for your patience.

Jun Tu said:
ospi_flash_dma

I am going through the ospi flash dma example workflow and then get back to your use case of writing/reading 256 kb of data.

Regards,

Vaibhav

0 Vaibhav Kumar over 1 year ago in reply to Jun Tu

TI__Guru 53553 points

Hello Jun,

Thanks for your patience.

I have seen the code you have written in the question description.

It would be really helpful if you could send me the project file itself so that I can run it on my setup and directly see the problem you are facing.

Looking forward to the project zip file.

Regards,

Vaibhav

0 Jun Tu over 1 year ago in reply to Vaibhav Kumar

Expert 1680 points

It won't work if we change from

#define APP_OSPI_FLASH_DMA_TEST_SIZE_BYTES (32U)
to

#define APP_OSPI_FLASH_DMA_TEST_SIZE_BYTES (256*1024U)

udmaChHandle_channel1 will be used to flash write to address 60800000.

. ospi_flash_dma.zip
I've uploaded the code please copy it under C:\ti\mcu_plus_sdk_am64x_09_01_00_41\examples\drivers\ospi

and compile with gmake -s -C .\

Also, the physical board to run is TMDS64EVM

Thanks

0 Vaibhav Kumar over 1 year ago in reply to Jun Tu

TI__Guru 53553 points

Hello Jun,

Thanks for providing the code file.

I have seen its taking a lot of time for execution(compared to 32) just by changing to 256 * 1024.

Please allow me sometime to report back with the results.

Regards,

Vaibhav

0 Vaibhav Kumar over 1 year ago in reply to Jun Tu

TI__Guru 53553 points

Hello Jun,

Thank you very much for your patience.

I think I would need to pull a DMA expert to comment further.

I am assigning this thread to one and you can expect responses in sometime.

Regards,

Vaibhav

0 Swargam Anil over 1 year ago in reply to Vaibhav Kumar

TI__Guru 51878 points

Hello Jun,

Currently, in MCU+SDK we don't support writing operations with the DMA.

But, we can do it and I can help you with that.

Can you please confirm you want this implementation in the SBL or Application ?

If it is in the SBL, then we won't enable DMA interrupt, and we will go in poling mode.

Jun Tu said:
However, Each time I can write only 1024 bytes.

Based on the above statement, the write operation is completed in 1024 bytes and not with 256 KBytes.

Can you please confirm you are doing the above testing in the SBL or ospi_dma_application ?

So, based on the above information, I don't need to start from scratch and if it is already working with 1024 bytes write writing, then I will provide suggestions to make work for 256KB write operations

Regards,

Anil.

0 Jun Tu over 1 year ago in reply to Swargam Anil

Expert 1680 points

Hi, Swargam,

"Can you please confirm you want this implementation in the SBL or Application ?"

actually we want it in application.

Can you please confirm you are doing the above testing in the SBL or ospi_dma_application ?

The above testing is done in the application,

needless to say before loading the software, I will load tools/ccsload/am64x/sciclient_ccs_init.release.out firstly. so sciclient should be sbl.

Thanks.

by the way, I found direct mode was not working with OSPI_writeDirect

. I mean if I config to direct mode and send "write enble" and then write 256 bytes (my page size is 256 bytes) to 0x60000000, it will not write in to the falsh.

0 Swargam Anil over 1 year ago in reply to Jun Tu

TI__Guru 51878 points

Hello Jun,

I can try to check at my side to create DMA Channel for writing operation and let you know the status in one to two days.

Regards,

Anil.

0 Swargam Anil over 1 year ago in reply to Swargam Anil

TI__Guru 51878 points

Hello Jun,

Status update : I have enabled DMA for OSPI write Channel as well.

During my testing I found that I was supposed to send 1KB/2KB but only 64 bytes transferred and I am debugging further.

Once this issue is fixed, I can try your requirement for transferring to 256KB.

Regards,

Anil.

0 Jun Tu over 1 year ago in reply to Swargam Anil

Expert 1680 points

I have same issue before, to solve it, it is dmss configuration. three dimensionnel setup.

0 Swargam Anil over 1 year ago in reply to Jun Tu

TI__Guru 51878 points

Hello Jun,

Can you please share your icnt and dicnt configuration working for write operation?

The OPSI device is a memory mapped device. So, what are we doing for read operation similarly we need to do for write operation.

Actually, in your case, you need to transfer 256 KB. So, we need to configure icnt0 and inct 1 . The maximum 256KB can't be written in to icnto since icnt values are 16bit, which can transfer the maximum 64KB only. So, we need to divide 256 KB in to two dimensions.

Regards,

Anil.

0 Jun Tu over 1 year ago in reply to Swargam Anil

Expert 1680 points

for sure, For that part I took udma example.

it works fine when I move 256k from msram to ddr.

but it doesn't work when I move 256k from ddr or msram to flash.

is it possible there some ospi config prevent us to write 256k. eg: auto polling,

For flash, we can write only one page in my case, one page is 256 bytes at a a time.

Thanks.

static void App_udmaTrpdInit(Udma_ChHandle chHandle,

uint32_t chIdx,

uint8_t *trpdMem,

const void *destBuf,

const void *srcBuf)

{

CSL_UdmapTR15 *pTr;

uint32_t cqRingNum = Udma_chGetCqRingNum(chHandle);

/* Make TRPD with TR15 TR type */

UdmaUtils_makeTrpdTr15(trpdMem, 1U, cqRingNum);

/* Setup TR */

pTr = UdmaUtils_getTrpdTr15Pointer(trpdMem, 0U);

pTr->flags = CSL_FMK(UDMAP_TR_FLAGS_TYPE, CSL_UDMAP_TR_FLAGS_TYPE_4D_BLOCK_MOVE_REPACKING_INDIRECTION);

pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_STATIC, 0U);

pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOL, CSL_UDMAP_TR_FLAGS_EOL_ICNT0_ICNT1);

pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EVENT_SIZE, CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT2_DEC);

pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0);

pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT2_DEC);

pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);

pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);

pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_CMD_ID, 0x25U); /* This will come back in TR response */

pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_SA_INDIRECT, 0U);

pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_DA_INDIRECT, 0U);

pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOP, 1U);

pTr->icnt0 = UDMA_TEST_1D_SIZE;

pTr->icnt1 = UDMA_TEST_2D_SIZE;

pTr->icnt2 = UDMA_TEST_3D_SIZE;

pTr->icnt3 = 1U;

pTr->addr = (uint64_t) Udma_defaultVirtToPhyFxn(srcBuf, 0U, NULL);

pTr->fmtflags = 0x00000000U; /* Linear addressing, 1 byte per elem */

pTr->dicnt0 = UDMA_TEST_1D_SIZE;

pTr->dicnt1 = UDMA_TEST_2D_SIZE;

pTr->dicnt2 = UDMA_TEST_3D_SIZE;

pTr->dicnt3 = 1U;

pTr->daddr = (uint64_t) Udma_defaultVirtToPhyFxn(destBuf, 0U, NULL);

if(0U == chIdx)

{

pTr->dim1 = pTr->icnt0;

pTr->dim2 = (pTr->icnt0 * pTr->icnt1);

pTr->dim3 = (pTr->icnt0 * pTr->icnt1 * pTr->icnt2);

pTr->ddim1 = pTr->dicnt0;

pTr->ddim2 = 0U;

pTr->ddim3 = 0U;

}

else

{

pTr->dim1 = pTr->icnt0;

pTr->dim2 = 0U;

pTr->dim3 = 0U;

pTr->ddim1 = pTr->dicnt0;

pTr->ddim2 = (pTr->dicnt0 * pTr->dicnt1);

pTr->ddim3 = (pTr->dicnt0 * pTr->dicnt1 * pTr->dicnt2);

}

/* Perform cache writeback */

CacheP_wb(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);

return;

}

0 Swargam Anil over 1 year ago in reply to Jun Tu

TI__Guru 51878 points

Jun Tu said:
it works fine when I move 256k from msram to ddr.

but it doesn't work when I move 256k from ddr or msram to flash.

Hello Jun ,

Ok, I thought you have tried to transfer data in between MSRAM or DDR to Flash.

As I mentioned above, I am able to write only 64 bytes and not able to write 1KB.

So, please give me some time. I can look at OSPI peripheral and NOR memory datasheet to help to figure out this issue and I will get back to you.

Regards,

Anil.

+1 Swargam Anil over 1 year ago in reply to Swargam Anil

TI__Guru 51878 points

Hello Jun ,

I have tried to enable DMA to write channel and it is not working.

Then, I internally checked with OSPI experts on this topic, and they confirmed that NOR flash will take more time to write page data as compared to read cycles and DMA does not have capability to poll the write operation is completed or not .

So, for the OSPI NOR flash types, even going with the DMA is not a benefit in the performance since, we need to poll whether to write operation is completed or not for every Page write .

Regards,

Anil.

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PROCESSOR-SDK-AM64X: ospi dma write 256KB problem. need help.