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OMAP L-137 putting SDRAM in self refresh mode in DSP bootloader

Armand Ciejak
Prodigy 170 points
Other Parts Discussed in Thread: DA8XX

I'm trying to set the SDRAM in  self refresh mode from the DSP bootloader without success.

I'm working on a custom board derived from the DA8XX EVAL board.

I have implemented what is documented in the SPRUFL7A in chapter 2.6.7, but the SDRAM goes into self refresh only if I execute the code via the JTAG emulator (either stepping through or just running). If I start the board with the exact same code but without the JTAG emulator connected the DSP bootloader hangs.

I added the following code to the DSP bootloader provided with the eval board:

// Set SDRFC register: LP_MODE = 1, MCLKSTOP_EN = 0, SR_PD = 0, REFRESH_RATE = keep original value
DDR->SDRCR = (DDR->SDRCR & 0x0000FFFF) | 0x80000000;

Any idea what could be wrong?

  • 0
    TI__Mastermind 27585 points

    Can you check to make sure TRST has an external pull down? This needs to be low during power up to ensure a POR, which initializes all internal registers.

    Jeff

  • 0 in reply to jc-ti
    Prodigy 170 points

    I've checked on the board and yes there is a pull down resistor (10k).

  • 0 in reply to Armand Ciejak
    Prodigy 170 points

    Here is the output of the GEL scripts:

    C674X_0: GEL Output:  ---------------------------------------------
    C674X_0: GEL Output: |             Device Information            |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: DEV_INFO_00 = 0x9B7DF02F
    C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_02 = 0x0000F3FB
    C674X_0: GEL Output: DEV_INFO_03 = 0x00000022
    C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
    C674X_0: GEL Output: DEV_INFO_06 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 8-0-62617-22-11-25
    C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 0,0,0,10369
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
    C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_19 =
    C674X_0: GEL Output: 0
    C674X_0: GEL Output: 0
    C674X_0: GEL Output: 0
    C674X_0: GEL Output: 0
    C674X_0: GEL Output: 0
    C674X_0: GEL Output: 
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
    C674X_0: GEL Output: DEV_INFO_21 = 0x3330306B
    C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
    C674X_0: GEL Output: -----
    C674X_0: GEL Output: DEV_INFO_24 = 0x1601900B
    C674X_0: GEL Output: DEV_INFO_25 = 0x0800F499
    C674X_0: GEL Output: DEV_INFO_06 = 0x00000000
    C674X_0: GEL Output: DEV_INFO_26 = 0x51020000
    C674X_0: GEL Output:  
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: |               BOOTROM Info                |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: ROM ID: d800k003 
    C674X_0: GEL Output: Silicon Revision 2.0
    C674X_0: GEL Output: Boot pins: 62459
    C674X_0: GEL Output: Boot Mode: UART1 (0x0000F3FB)
    C674X_0: GEL Output:  ROM Status Code: 0x0000001B  Description:
    C674X_0: GEL Output: SDMMC read error
    C674X_0: GEL Output:  Program Counter (PC) = 0x00712144
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: |              PSC0 Information             |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: 
    C674X_0: GEL Output: State Decoder:
    C674X_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
    C674X_0: GEL Output:  1 = SyncReset (reset assered, clock on)
    C674X_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
    C674X_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
    C674X_0: GEL Output: >3 = Transition in progress
    C674X_0: GEL Output: 
    C674X_0: GEL Output: Module 0:    EDMA3CC (0)        STATE = 0
    C674X_0: GEL Output: Module 1:    EDMA3 TC0          STATE = 0
    C674X_0: GEL Output: Module 2:    EDMA3 TC1          STATE = 0
    C674X_0: GEL Output: Module 3:    EMIFA (BR7)        STATE = 0
    C674X_0: GEL Output: Module 4:    SPI 0              STATE = 0
    C674X_0: GEL Output: Module 5:    MMC/SD 0           STATE = 0
    C674X_0: GEL Output: Module 6:    AINTC              STATE = 3
    C674X_0: GEL Output: Module 7:    ARM RAM/ROM        STATE = 3
    C674X_0: GEL Output: Module 9:    UART 0             STATE = 0
    C674X_0: GEL Output: Module 10:    SCR 0 (BR0/1/2/8)  STATE = 3
    C674X_0: GEL Output: Module 11:    SCR 1 (BR4)        STATE = 3
    C674X_0: GEL Output: Module 12:    SCR 2 (BR3/5/6)    STATE = 3
    C674X_0: GEL Output: Module 13:    PRUSS              STATE = 0
    C674X_0: GEL Output: Module 14:    ARM                STATE = 0
    C674X_0: GEL Output: Module 15:    DSP                STATE = 3
    C674X_0: GEL Output: 
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: |              PSC1 Information             |
    C674X_0: GEL Output: ---------------------------------------------
    C674X_0: GEL Output: 
    C674X_0: GEL Output: State Decoder:
    C674X_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
    C674X_0: GEL Output:  1 = SyncReset (reset assered, clock on)
    C674X_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
    C674X_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
    C674X_0: GEL Output: >3 = Transition in progress
    C674X_0: GEL Output: 
    C674X_0: GEL Output: Module 1:    USB0 (2.0)         STATE = 0
    C674X_0: GEL Output: Module 2:    USB1 (1.1)         STATE = 0
    C674X_0: GEL Output: Module 3:    GPIO               STATE = 0
    C674X_0: GEL Output: Module 4:    UHPI               STATE = 0
    C674X_0: GEL Output: Module 5:    EMAC               STATE = 0
    C674X_0: GEL Output: Module 6:    EMIFB (BR20)       STATE = 3
    C674X_0: GEL Output: Module 7:    MCASP0 + FIFO      STATE = 0
    C674X_0: GEL Output: Module 8:    MCASP1 + FIFO      STATE = 0
    C674X_0: GEL Output: Module 9:    MCASP2 + FIFO      STATE = 0
    C674X_0: GEL Output: Module 10:    SPI 1              STATE = 0
    C674X_0: GEL Output: Module 11:    I2C 1              STATE = 0
    C674X_0: GEL Output: Module 12:    UART 1             STATE = 3
    C674X_0: GEL Output: Module 13:    UART 2             STATE = 0
    C674X_0: GEL Output: Module 16:    LCDC               STATE = 0
    C674X_0: GEL Output: Module 17:    eHRPWM (all)       STATE = 0
    C674X_0: GEL Output: Module 20:    eCAP (all)         STATE = 0
    C674X_0: GEL Output: Module 21:    eQEP 0/1           STATE = 0
    C674X_0: GEL Output: Module 24:    SCR8 (Br15)        STATE = 3
    C674X_0: GEL Output: Module 25:    SCR7 (Br12)        STATE = 3
    C674X_0: GEL Output: Module 26:    SCR12 (Br18)       STATE = 3
    C674X_0: GEL Output: Module 31:    L3 RAM (Br13)      STATE = 3

  • 0 in reply to Armand Ciejak
    TI__Mastermind 27585 points

    The error you are seeing 0x1B (the GEL file incorrectly calls this MMCSD error) can only occur after the entire bootloading process has finished. Can you check a few things and get back to us?

    1) Put and IDLE instruction or a while(1) at the very start of your code. After you boot you should see the PC there. We need to eliminate the possibility that something in your code is causing it to jump back to the bootloader

    2) If you reset the board with power still applied, does the boot still fail in the same way?

    3) If the boot fails, check to see if the code got loaded to the specific memory locations or not.

    Jeff

  • 0 in reply to jc-ti
    Prodigy 170 points

    Thanks for your advices, they lead me to the problem: the DSP bootloader entry point was hard coded, which means that any change made to the original code was making the DSP bootloader to jump back to the ROM bootloader because the entry point was not the hard coded one. I fixed that and I can successfully put the SDRAM in self-refresh.