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DDR3 PHY calculation spreadsheet for TMS320C6678

maril
Intellectual 560 points

Other Parts Discussed in Thread: TMS320C6678

Hi All ,

The DDR3 Memory controller user guide document (sprugv8b.pdf) for keystone devices mentions "PHY calculation spreadsheet" that can be used to generate values to programm the boot congiguration registers during write/read levelling configuration. However , i am not able to locate this spreadsheet. Can someone please point me to this spreadsheet for TMS320C6678 processor.

Thanks in advance,

-Anil

 

  • 0
    TI__Expert 6815 points

    Maril,

    We are in the process of migrating the document to external web. Till then, please use the attached version that will eventually be migrated to ti.com.

    Regards,

    Aditya

    DDR3 PHY Calc v8.xls
  • 0 in reply to Aditya
    Intellectual 560 points

    Hi Aditya,

    Thanks a lot for the info.

    -Anil

     

     

  • 0 in reply to maril
    Intellectual 560 points

    Hi Aditya ,

    In our custom board housing TMS320C6678 processor we are using a single DDR3 device interfaced to the processor. The DDR3 device is a 128MX16 part.

    Do we need to enable software levelling in our case ? How do we use the DDR3 PHY Calculation excel sheet for our board? What should be the values to be programmed  for the unused byte lanes ? Entering a value 0 does not provide valid initial values for levelling.

    -Anil

  • 0 in reply to maril
    TI__Expert 6815 points

    Anil,

    Although leveling is enabled and triggered in software via memory mapped registers, what it really triggers is hardware leveling inside the DDR PHY. For your setup, you can enter the routing lengths for DQS & CK for byte lanes 0 & 1 in the PHY calc spreadsheet and use the init ratios you get from the spreadsheet. Please note that DATA7_* is actually byte lane 0, DATA6_* is byte lane 1...and DATA0 is byte lane 7. DATA8_* is the ECC byte lane.

    You can enter 0s for unused byte lanes. Since the leveling algorithm levels each byte lane independently it will be a don't care.

  • 0 in reply to Aditya
    Intellectual 475 points

    Hi Aditya,

    I am working on a DM8148 with a DDR3-1333 that is a different speed than the TI reference design.

    I am encountering some difficulties to set up the timing of the DDR3 PHY, I have seen that you provide a nice spreadsheet tool for custom board DDR3 configuration,

    Is this spreadsheet exist also for the DM8148 chip?

    If yes, I 'll be pleased if you could share it with me.

    Thanks,

    Jonathan

  • 0 in reply to Jonathan Journo
    TI__Expert 6815 points

    Hi Jonathan,

    Unfortunately I work in a different group so I don't support DaVinci processors. I think you are likely to find support in the  DM814x and AM387x Processors Forum.

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716.aspx