Hi,
I'm trying to bring up a new AM3505 board that boots from an 8-bit NAND flash, and it doesn't boot.
I made the changes listed below to convert the BSP to 8-bit from 16-bit, and I use pserial.exe to download
the XLDR - which in turn downloads my AM35x-nand.raw file. That part works OK.
On reset, I get the "40X" on the serial port after I download the raw file, so I know the ROM doesn't
like what it is seeing in flash.
I have modified the XLDR to read back the data I programmed, and it looks good. I also have a Signum JTAG JET
which Chameleon sometimes shows me the XLDR loaded into address 0x40200000, but I'm getting sick of stepping
through the ROM to find out what I did wrong.
Any help in what to look at would be greatly appreciated.
Thanks,
--Jason
Details:
Micron 8-bit flash: MT29F4G08ABADAWP
Wince 7 BSP_WINCE_ARM_A8-1.00.00.09
Cloned C:\WINCE700\platform\AM35x_BSP into local platform BSP
Ported C:\WINCE700\platform\common\src\soc\COMMON_TI_V1\COMMON_TI\BLOCK\NAND into my local platform.
I verified that XLDR and EBOOT NAND link againsts my fmd_nand_boot.lib
I set BSP_OMAP_NAND_ECC_HAMMING1BIT = 1 in my project environment
Then I modified the following files to enable 8-bit flash:
bspcfg.c:
---------
NAND_INFO SupportedNands[] = {
#ifdef REF_BOARD
{
0x2C, //manufacturerId
0xBA, //deviceId
2048, //blocks
64, //sectorsPerBlock
2048, //sectorSize
2 //wordData
}
,
{
0x2C, //manufacturerId
0xBC, //deviceId
2048, //blocks
64, //sectorsPerBlock
2048, //sectorSize
2 //wordData
}
#else // my BSP
{
0x2C, //manufacturerId
0xDC, //deviceId // 8 bit ID
2048, //blocks
64, //sectorsPerBlock
2048, //sectorSize
4 //wordData // 8 bit is 1 byte
}
#endif
};
fmd.c:
------
redefined access macros:
// nand access definitions
#define WRITE_NAND(x,y) OUTREG8(x,y) // 8-bit access
#define READ_NAND(x) INREG8(x) // 8-bit access
typedef REG8 NANDREG;
modified ECC location by removing 1 byte
//------------------------------------------------------------------------------
// NAND Spare Area Format for x16 devices
/* 16 bit access, large page nand */
typedef struct
{
#ifdef MICRON_16_BIT_FLASH
UCHAR hwBadBlock[2]; // Hardware bad block flag
#else
UCHAR hwBadBlock; // Hardware bad block flag
#endif
UCHAR ecc[ECC_BYTES]; //BootROM expect ECC starts from the 3rd byte when bus width is 16
UCHAR reserved1[4]; // Reserved - used by FAL
UCHAR reserved2[2]; // Reserved - used by FAL
UCHAR swBadBlock; // Software bad block flag
UCHAR oemReserved; // For use by OEM
UCHAR unused[2]; // Unused
}NAND_SPARE_AREA;
in function NAND_Initialize:
#ifdef NAND_16_BIT
/* ECCCfg: 16bit bus width, cs0, 4 - 512 bytes blocks per page */
pDevice->ECCCfg = (GPMC_ECC_CONFIG_16BIT | (chipSelect << 1) | (0x3<<4));
pDevice->ECCsize = (pDevice->ECCtype == Hamming1bit ) ? ECC_BYTES_HAMMING :
(pDevice->ECCtype == BCH4bit ) ? ECC_BYTES_BCH4 : ECC_BYTES_BCH8;
#else
pDevice->ECCCfg = (GPMC_ECC_CONFIG_8BIT | (chipSelect << 1) | (0x3<<4));
pDevice->ECCsize = (pDevice->ECCtype == Hamming1bit ) ? ECC_BYTES_HAMMING :
(pDevice->ECCtype == BCH4bit ) ? ECC_BYTES_BCH4 : ECC_BYTES_BCH8;
#endif
in function FMD_ReadSector, used new BadBlock data size:
#ifdef MICRON_16_BIT_FLASH
pSectorInfo->bBadBlock = sa.hwBadBlock[0] & sa.hwBadBlock[1]; // HW bad block check
#else
pSectorInfo->bBadBlock = sa.hwBadBlock; // HW bad block check
#endif
in function FMD_WriteSector, used new BadBlock data size:
// Fill in rest of spare area info (we already have ECC from above)
#ifdef MICRON_16_BIT_FLASH
sa.hwBadBlock[0] = pSectorInfo->bBadBlock;
sa.hwBadBlock[1] = pSectorInfo->bBadBlock;
#else
sa.swBadBlock = pSectorInfo->bBadBlock;
#endif