TDA4VH-Q1: PCIe 2L support

Hi,

You can find more details about SerDes Pins mapping from TRM.
Below is capture from TRM. Where it highlights yellow marked will be 2x4L PCIe.
The round circled will be 4x2L PCIe (i.e.  2Lanes PCIe of 4 instances)


Best Regards,
Sudheer

Hi Xingyu,

To add on to Sudheer's response, Table 5.1 in the datasheet (https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf) has which pins on the SoC are for PCIe1 lane 0, 1, 2, 3, etc: 

We also provide a reference board that can be used when designing your custom board, and this can be used for which pins are for which PCIe controller and lane. The reference board design can be found on the EVM purchase page: https://www.ti.com/tool/J784S4XEVM, and it is under "Design files" section.

And lastly, in terms of software, this file is a good reference to see what other peripherals share the SERDES lanes: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/include/dt-bindings/mux/ti-serdes.h?h=ti-linux-6.1.y. Anything that is J784S4 is for the TDA4VH/AM69.

Regards,

Takuma