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OMAPL138 Master Priorities

Marc48067
Expert 2000 points

Other Parts Discussed in Thread: OMAPL138

Hello,

I've got a simple question about master priority and bus arbitration on the OMAPL138. It is mentioned that large edma transfers shouldn' be done at a high master priority level in order to not lock out low prioriy transfers from other masters to the same slave for a long time. As far as I know the large edma transfer is splitted into several burst. The question now is whether there are slots for the other low priority masters between each burst or if the bus is locked until the large transfer completes.

Thanks for your efforts

  • 0
    TI__Guru* 85245 points

    Marc48067 said:
    As far as I know the large edma transfer is splitted into several burst. The question now is whether there are slots for the other low priority masters between each burst or if the bus is locked until the large transfer completes.

    You are correct that a transfer request packet, will be internally broken down into EDMA burst size chunks ( 16, 32 or 64 bytes , which is configurable), however if you are doing these transfers between "fast" end points e.g a memory to memory transfers (internal/shared RAM etc), the chances are likely that all these bursts will be submitted back to back , providing little down time and lower probability of having the lower priority transfers to slip in, therefore it would be better to change the EDMA transfer to break into smaller chunks (smaller transfer request packets) and/or if your other masters are important you can make them the same priority as the EDMA transfer controllers.

    Regards

    Mukul