SK-TDA4VM: flickering every 5 sec when connected DP,

Hi,

Can you please confirm that you are applying QoS changes in the SDK, for using DSS output for such a large resolution? 

Regards,

Brijesh

Hi,

How can I check if QoS chnages are applied in the SDK?

And how can I change DP output resolution?

I checked it on 2 mointors.

- LG(UHD-3840x2160): Flickering

- ThinkVision(QHD-2560x1440): No flickering

FYI, we are using ti-processor-sdk-linux-edgeai-j721e-evm-09_01_00_06-Linux-x86.

JB

Hi JB,

Not sure about edgeAI, but can you please check if your uboot source included arch/arm/mach-k3/include/mach/j721e_qos_params.h and changes in the arch/arm/mach-k3/j721e_init.c to set up QoS parameter?

Regards,

Brijesh

Hi Brijesh,

I checked 'arch/arm/mach-k3/j721e_init.c' included 'arch/arm/mach-k3/include/mach/j721e_qos_params.h',
and I appended log message(refer to the following modification) and found it in booting logs.

diff --git a/linux/board-support/ti-u-boot-2023.04+gitAUTOINC+71b8c840ca-g71b8c840ca/arch/arm/mach-k3/j721e_init.c b/linux/board-support/ti-u-boot-2023.04+gitAUTOINC+71b8c840ca-g71b8c840ca/arch/arm/mach-k3/j721e_init.c
index ec0d97669..e0fb1f22c 100644
--- a/linux/board-support/ti-u-boot-2023.04+gitAUTOINC+71b8c840ca-g71b8c840ca/arch/arm/mach-k3/j721e_init.c
+++ b/linux/board-support/ti-u-boot-2023.04+gitAUTOINC+71b8c840ca-g71b8c840ca/arch/arm/mach-k3/j721e_init.c
@@ -562,6 +562,7 @@ void board_init_f(ulong dummy)
 #endif
 
 	if (soc_is_j721e()) {
+		printf("|JCP| setup qos ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n");
 		setup_navss_nb();
 		setup_c66_qos();
 		setup_main_r5f_qos();

BTW, how can I change DP output resolution?
Is there any command for resolution?

Regards,
JB

Hi JB,

Can you please check if any of above code is setting up DSS QoS? Because if the DSS QoS is setup, there should not be "SyncLost" error..

i am not sure how to change resolution on Linux. 

Regards,

Brijesh 

Hi Brijesh,

There is setup_dss_qos(), and it is called by board_init_f().

void setup_dss_qos(void)
{
	unsigned int channel, group;

	printf("|JCP| setup_dss_qos() ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n");

	/* two master ports: dma and fbdc */
	/* two groups: SRAM and DDR */
	/* 10 channels: (pipe << 1) | is_second_buffer */

	/* master port 1 (dma) */
	for (group = 0; group < QOS_DSS0_DMA_NUM_J_CH; ++group) {
		writel(0x76543210, (uintptr_t)QOS_DSS0_DMA_CBASS_GRP_MAP1(group));
		writel(0xfedcba98, (uintptr_t)QOS_DSS0_DMA_CBASS_GRP_MAP2(group));
	}

	for (channel = 0; channel < QOS_DSS0_DMA_NUM_I_CH; ++channel) {

		writel((QOS_DSS0_DMA_ATYPE << 28) | (QOS_DSS0_DMA_PRIORITY << 12) | (QOS_DSS0_DMA_ORDER_ID << 4), (uintptr_t)QOS_DSS0_DMA_CBASS_MAP(channel));
	}

	/* master port 2 (fbdc) */
	for (group = 0; group < QOS_DSS0_FBDC_NUM_J_CH; ++group) {
		writel(0x76543210, (uintptr_t)QOS_DSS0_FBDC_CBASS_GRP_MAP1(group));
		writel(0xfedcba98, (uintptr_t)QOS_DSS0_FBDC_CBASS_GRP_MAP2(group));
	}

	for (channel = 0; channel < QOS_DSS0_FBDC_NUM_I_CH; ++channel) {

		writel((QOS_DSS0_FBDC_ATYPE << 28) | (QOS_DSS0_FBDC_PRIORITY << 12) | (QOS_DSS0_FBDC_ORDER_ID << 4), (uintptr_t)QOS_DSS0_FBDC_CBASS_MAP(channel));
	}
}

Regards,
JB

Hi JB,

That's strange. If QoS for DSS is setup correctly, there should not be any sync lost error. Can you please check if also setup_navss_nb API is getting called? 

Also, can we readback few of these DSS QoS registers and confirm they are set? 

Regards,

Brijesh

Hi Brijesh,

I checked that setup_navss_nb() was called, and readback DSS QoS registers in u-boot mode.
Some registers' value are not matched between writing and reading.
(write: 0x00001090 but read: 0x00000090)

Please refer to the following logs,

U-Boot SPL 2023.04 (Jul 15 2024 - 10:04:27 +0900)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.2--v09.01.02 (Kool Koala)')
|JCP| setup qos ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|JCP| setup_navss_nb() ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|JCP| setup_dss_qos() ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|JCP| setup_dss_qos(): master port 1 (dma)
writel(0x76543210, 0x45dc2000)
writel(0xfedcba98, 0x45dc2004)
writel(0x76543210, 0x45dc2008)
writel(0xfedcba98, 0x45dc200c)
writel(0x00001090, 0x45dc2100)
writel(0x00001090, 0x45dc2104)
writel(0x00001090, 0x45dc2108)
writel(0x00001090, 0x45dc210c)
writel(0x00001090, 0x45dc2110)
writel(0x00001090, 0x45dc2114)
writel(0x00001090, 0x45dc2118)
writel(0x00001090, 0x45dc211c)
writel(0x00001090, 0x45dc2120)
writel(0x00001090, 0x45dc2124)
|JCP| setup_dss_qos(): master port 2 (fbdc)
writel(0x76543210, 0x45dc2400)
writel(0xfedcba98, 0x45dc2404)
writel(0x76543210, 0x45dc2408)
writel(0xfedcba98, 0x45dc240c)
writel(0x00001090, 0x45dc2500)
writel(0x00001090, 0x45dc2504)
writel(0x00001090, 0x45dc2508)
writel(0x00001090, 0x45dc250c)
writel(0x00001090, 0x45dc2510)
writel(0x00001090, 0x45dc2514)
writel(0x00001090, 0x45dc2518)
writel(0x00001090, 0x45dc251c)
writel(0x00001090, 0x45dc2520)
writel(0x00001090, 0x45dc2524)
Trying to boot from MMC2
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted


U-Boot 2023.04 (Jul 15 2024 - 10:04:27 +0900)

SoC:   J721E SR1.1 GP
Model: Texas Instruments J721E SK A72
Board: J721EX-EAIK rev A1
->software_revision: 01
->serial: 1358
->mac_addr_cnt: 0
DRAM:  4 GiB
Core:  121 devices, 34 uclasses, devicetree: separate
Flash: 0 Bytes
MMC:   mmc@4fb0000: 1
Loading Environment from nowhere... OK
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
Net:   eth0: ethernet@46000000port@1
Hit any key to stop autoboot:  2  1  0 
=> 


=> echo 'master port 1 (dma)...'
master port 1 (dma)...
=> md.l 0x45dc2000 1
45dc2000: 76543210                             .2Tv
=> md.l 0x45dc2004 1
45dc2004: fedcba98                             ....
=> md.l 0x45dc2008 1
45dc2008: 76543210                             .2Tv
=> md.l 0x45dc200c 1
45dc200c: fedcba98                             ....
=> md.l 0x45dc2100 1
45dc2100: 00000090                             ....
=> md.l 0x45dc2104 1
45dc2104: 00000090                             ....
=> md.l 0x45dc2108 1
45dc2108: 00000090                             ....
=> md.l 0x45dc210c 1
45dc210c: 00000090                             ....
=> md.l 0x45dc2110 1
45dc2110: 00000090                             ....
=> md.l 0x45dc2114 1
45dc2114: 00000090                             ....
=> md.l 0x45dc2118 1
45dc2118: 00000090                             ....
=> md.l 0x45dc211c 1
45dc211c: 00000090                             ....
=> md.l 0x45dc2120 1
45dc2120: 00000090                             ....
=> md.l 0x45dc2124 1
45dc2124: 00000090                             ....
=> echo 'master port 2 (fbdc)...'
master port 2 (fbdc)...
=> md.l 0x45dc2400 1
45dc2400: 76543210                             .2Tv
=> md.l 0x45dc2404 1
45dc2404: fedcba98                             ....
=> md.l 0x45dc2408 1
45dc2408: 76543210                             .2Tv
=> md.l 0x45dc240c 1
45dc240c: fedcba98                             ....
=> md.l 0x45dc2500 1
45dc2500: 00000090                             ....
=> md.l 0x45dc2504 1
45dc2504: 00000090                             ....
=> md.l 0x45dc2508 1
45dc2508: 00000090                             ....
=> md.l 0x45dc250c 1
45dc250c: 00000090                             ....
=> md.l 0x45dc2510 1
45dc2510: 00000090                             ....
=> md.l 0x45dc2514 1
45dc2514: 00000090                             ....
=> md.l 0x45dc2518 1
45dc2518: 00000090                             ....
=> md.l 0x45dc251c 1
45dc251c: 00000090                             ....
=> md.l 0x45dc2520 1
45dc2520: 00000090                             ....
=> md.l 0x45dc2524 1
45dc2524: 00000090                             ....

Regards,
JB

Hi JB,

Can you please readback these registers from Linux prompt? I am wondering if there is any change in the Linux. 

Ideally, if these settings are set, we should not have seen DSS SyncLost error.  Are you also running capture driver in parallel or running anything on Main Domain R5F? 

Regards,

Brijesh 

Hi Brijesh,

How can I readback these registers in Linux prompt?

And I just run the Edge AI gallery.

How can I check if running capture driver in parallel or running anything on Main Domain R5F?

Regards,
JB

Maybe you can connect to the board using Ethernet and do telnet this board to read these registers? 

Regards,

Brijesh

Hi Brijesh,

I readback w/ devmem2 and same values as read in u-boot.

master port 1 (dma)
Read at address  0x45DC2000 (0xffff82ac2000): 0x76543210
Read at address  0x45DC2004 (0xffff9e507004): 0xFEDCBA98
Read at address  0x45DC2008 (0xffffa2eb1008): 0x76543210
Read at address  0x45DC200C (0xffff9e58500c): 0xFEDCBA98
Read at address  0x45DC2100 (0xffff98fec100): 0x00000090
Read at address  0x45DC2104 (0xffff87859104): 0x00000090
Read at address  0x45DC2108 (0xffffb59c7108): 0x00000090
Read at address  0x45DC210C (0xffffabea410c): 0x00000090
Read at address  0x45DC2110 (0xffffba473110): 0x00000090
Read at address  0x45DC2114 (0xffffbb5fd114): 0x00000090
Read at address  0x45DC2118 (0xffff8f7ce118): 0x00000090
Read at address  0x45DC211C (0xffffba85811c): 0x00000090
Read at address  0x45DC2120 (0xffff83cab120): 0x00000090
Read at address  0x45DC2124 (0xffffb48d0124): 0x00000090
master port 2 (fbdc)
Read at address  0x45DC2400 (0xffff91a07400): 0x76543210
Read at address  0x45DC2404 (0xffffbec65404): 0xFEDCBA98
Read at address  0x45DC2408 (0xffffb4789408): 0x76543210
Read at address  0x45DC240C (0xffff91fee40c): 0xFEDCBA98
Read at address  0x45DC2500 (0xffff98e27500): 0x00000090
Read at address  0x45DC2504 (0xffff95745504): 0x00000090
Read at address  0x45DC2508 (0xffff80a65508): 0x00000090
Read at address  0x45DC250C (0xffff80d0c50c): 0x00000090
Read at address  0x45DC2510 (0xffff8399c510): 0x00000090
Read at address  0x45DC2514 (0xffff86a48514): 0x00000090
Read at address  0x45DC2518 (0xffff8640c518): 0x00000090
Read at address  0x45DC251C (0xffff810aa51c): 0x00000090
Read at address  0x45DC2520 (0xffff85e2c520): 0x00000090
Read at address  0x45DC2524 (0xffff85cfa524): 0x00000090

Regards,
JB

Hi JB,

Can you also readback value at 0x3803010? It must be set to 0x2. 

Regards,

Brijesh

Hi Brijesh,

0x3803010 is 0x02.

# devmem2 0x3803010 | grep Read
Read at address 0x03803010 (0xffff8cf1a010): 0x00000002

Regards,
JB

Hi,

Strange, what else are you running in the system? I am just wondering if any other core processing is affecting DSS. There shouldn't be any synclost error. 

Regards,

Brijesh

Hi Brijesh,

The edgeai-gui-app  - demo application of EVM(SK-TDA4VM) - is running.
I didn't run anything else.

Regards,
JB

Hi JB,

That's strange. let me check if there is any more registers that need to be tuned. 

Regards,

Brijesh

Hi JB,

Which video pipeline are you using? Can you please share the value of BUF_THRESHOLD register of this pipeline? 

Regards,

Brijesh

Hi Brijesh,

DSS0_VID_BUF_THRESHOLD:
Read at address 0x04A2003C (0xffffa29e303c): 0x0FFF0800
Read at address 0x04A3003C (0xffff8aa7003c): 0x0FFF0800
Read at address 0x04A5003C (0xffffbd52103c): 0x0FFF0800
Read at address 0x04A6003C (0xffffbf0f503c): 0x0FFF0800

Regards,
JB

Hi JB,

Can you try changing lower threshold to some higher value like 0xF00, instead of 0x800?

Regards,

Brijesh

Hi Brijesh,

I changed threshold to higer value that you suggested, but still flickering. 

DSS0_VID_BUF_THRESHOLD:
Write at address 0x04A2003C (0xffffbe70203c): 0x0FFF0F00, readback 0x0FFF0F00
Write at address 0x04A3003C (0xffff8931003c): 0x0FFF0F00, readback 0x0FFF0F00
Write at address 0x04A5003C (0xffffbf38603c): 0x0FFF0F00, readback 0x0FFF0F00
Write at address 0x04A6003C (0xffffa053c03c): 0x0FFF0F00, readback 0x0FFF0F00

Regards,

Brijesh

Hi JB,

Do you see synclost error only when it is flickering or the other way? 

Also can you please readback the below register's value and share them?

0x45D84100

0x45D84500

0x45D84900

0x45D84D00

Regards,

Brijesh

Hi Brijesh,

Please check the following,

and registers' value,

Read Registers:
Read at address  0x45D84100 (0xffff9ab98100): 0x000020B0
Read at address  0x45D84500 (0xffffa8b74500): 0x000020B0
Read at address  0x45D84900 (0xffff824db900): 0x000020B0
Read at address  0x45D84D00 (0xffffa6821d00): 0x000020B0

Regards,

JB

Hi JB,

Can you please change value of these all registers to 0x00002050?

Regards,

Brijesh

Hi Brijesh,

I changed all the registers to 0x00002050, but still flickering.

Write Registers:
Write at address 0x45D84100 (0xffff92b59100): 0x00002050, readback 0x00002050
Write at address 0x45D84500 (0xffff915f3500): 0x00002050, readback 0x00002050
Write at address 0x45D84900 (0xffff92420900): 0x00002050, readback 0x00002050
Write at address 0x45D84D00 (0xffffb1cf3d00): 0x00002050, readback 0x00002050

[ 73.480686] tidss 4a00000.dss: CRTC0 SYNC LOST: (irq 80)
[ 73.858309] tidss 4a00000.dss: CRTC0 SYNC LOST: (irq 80)
[ 75.809393] tidss 4a00000.dss: CRTC0 SYNC LOST: (irq 80)
...

Regards,

JB

Hi JB,

ok, what's the value at the offset 0x04A00098?

Regards,

Brijesh

Hi Brijesh,

# devmem2 0x04A00098
/dev/mem opened.
Memory mapped at address 0xffff809d9000.
Read at address  0x04A00098 (0xffff809d9098): 0x00000002

Regards,

JB

Hi JB,

MFLAG is enabled, Fifo threshold are setup properly, QoS is setup properly for the DSS pipelines, then we should not see sync lost errors. there are the only things that can affect DSS read path. 

Is it possible to reproduce this issue on EVM? 

Regards,

Brijesh

Hi Brijesh,

Up  to now, I have tested(read/write registers)  on EVM, and reproduced it.

Regards,

JB

Hi JB,

I mean, can you please share the exact setup, SDK, version etc information to reproduce this issue? 

Regards,

Brijesh 

Hi Brijesh,

Please refer to the followings,

- ti-processor-sdk-linux-edgeai-j721e-evm-09_01_00_06-Linux-x86.bin

- connect EVM to LG(UHD-3840x2160) monitor via DP

- booting and running Edge AI gallery (edgeai-init.service) automatically, then flickering

Regards,

JB

Hi JB,

ok i will try to check it out next week.

Regards,

Brijesh