PROCESSOR-SDK-J784S4: SerDes Configuration

Daniel Braunwarth

Tool/software:

We would like to configure the following SerDes layout with SDK 9.2 in the Linux kernel:

Serdes 0-0 PCIe1
Serdes 0-2 PCIe3
Serdes 1-0 PCIe0
Serdes 1-2 PCIe2
Serdes 2-0 SGMII
Serdes 2-1 SGMII
Serdes 2-2 QSGMII
Serdes 2-3 SGMII
Serdes 4-2 SGMII
Serdes 4-3 USB3

Currently we are having the following device tree:

&serdes0 {
	status = "okay";
	serdes0_pcie1_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>;
	};

	serdes0_pcie3_link: phy@2 {
		reg = <2>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 3>;
	};
};

&serdes_wiz0 {
	status = "okay";
};

&serdes1 {
	status = "okay";
	serdes1_pcie0_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz1 1>;
	};

	serdes1_pcie2_link: phy@2 {
		reg = <2>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz1 3>;
	};
};

&serdes_wiz1 {
	status = "okay";
};

&serdes2 {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	serdes2_sgmii_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
	};

	serdes2_qsgmii_link: phy@2 {
		reg = <2>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_QSGMII>;
		resets = <&serdes_wiz2 3>;
	};

	serdes2_qsgmii_link2: phy@3 {
		reg = <3>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz2 4>;
	};
};

&serdes_wiz2 {
	status = "okay";
};

&serdes4 {
	status = "okay";

	serdes4_sgmii_link: phy@2 {
		reg = <2>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz4 3>;
	};

	serdes4_usb_link: phy@3 {
		reg = <3>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz4 4>;
	};
};

&serdes_wiz4 {
	status = "okay";
};

/* refer to include/dt-bindings/mux/ti-serdes.h */
&serdes_ln_ctrl {
	mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
			<0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
			<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
			<0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
			<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
			<0x40a8 0x3>, <0x40ac 0x3>, /* SERDES2 lane2/3 select */
			<0x40c0 0x3>, <0x40c4 0x3>, /* SERDES4 lane0/1 select */
			<0x40c8 0x3>, <0x40cc 0x3>; /* SERDES4 lane2/3 select */

	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,   /* PCIe1 */
		      <J784S4_SERDES0_LANE1_IP3_UNUSED>,
		      <J784S4_SERDES0_LANE2_PCIE3_LANE0>,   /* PCIe3 */
		      <J784S4_SERDES0_LANE3_IP4_UNUSED>,
		      <J784S4_SERDES1_LANE0_PCIE0_LANE0>,   /* PCIe0 */
		      <J784S4_SERDES1_LANE1_IP3_UNUSED>,
		      <J784S4_SERDES1_LANE2_PCIE2_LANE0>,   /* PCIe2 */
		      <J784S4_SERDES1_LANE3_IP4_UNUSED>,
		      <J784S4_SERDES2_LANE0_QSGMII_LANE5>,  /* SGMII: RTL8211 */
		      <J784S4_SERDES2_LANE1_QSGMII_LANE6>,  /* SGMII: RTL8211 */
		      <J784S4_SERDES2_LANE2_QSGMII_LANE1>,  /* QSGMII: YT8614 */
		      <J784S4_SERDES2_LANE3_QSGMII_LANE2>,  /* SGMII: RTL8211 */ /* TODO Maybe J784S4_SERDES2_LANE3_QSGMII_LANE8 ?*/
		      <J784S4_SERDES4_LANE0_IP3_UNUSED>,
		      <J784S4_SERDES4_LANE1_IP3_UNUSED>,
		      <J784S4_SERDES4_LANE2_QSGMII_LANE7>,  /* SGMII: RTL8211 */
		      <J784S4_SERDES4_LANE3_USB>;           /* USB */
};

&serdes_refclk {
	clock-frequency = <100000000>;
};

&pcie0_rc {
	status = "okay";
	num-lanes = <1>;
	phys = <&serdes1_pcie0_link>;
	phy-names = "pcie-phy";
};

&pcie1_rc {
	status = "okay";
	num-lanes = <1>;
	phys = <&serdes0_pcie1_link>;
	phy-names = "pcie-phy";
};

&pcie2_rc {
	status = "okay";
	num-lanes = <1>;
	phys = <&serdes1_pcie2_link>;
	phy-names = "pcie-phy";
};

&pcie3_rc {
	status = "okay";
	num-lanes = <1>;
	phys = <&serdes0_pcie3_link>;
	phy-names = "pcie-phy";
};

/* Main CPSW9G */
&cpsw0_phy_gmii_sel {
	ti,qsgmii-main-ports = <1>, <1>;
};

&main_cpsw0 {
	status = "okay";
	pinctrl-names = "default";
};

/* EEXB TP [YT8614] */
&main_cpsw0_port1 {
	status = "okay";
	phy-handle = <&cpsw9g_phy0>;
	phy-mode = "qsgmii";
	local-mac-address = [02 60 C8 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 1>;
	phy-names = "mac";
};

/* KSI (XF1) [YT8614] */
&main_cpsw0_port2 {
	status = "okay";
	phy-handle = <&cpsw9g_ksi>;
	phy-mode = "qsgmii";
	local-mac-address = [02 60 C8 00 00 01];
	phys = <&cpsw0_phy_gmii_sel 2>;
	phy-names = "mac";
};

/* TP [YT8614] */
&main_cpsw0_port3 {
	status = "okay";
	phy-handle = <&cpsw9g_tp>;
	phy-mode = "qsgmii";
	local-mac-address = [02 60 C8 00 00 02];
	phys = <&cpsw0_phy_gmii_sel 3>;
	phy-names = "mac";
};

/* DIOB [YT8614] */
&main_cpsw0_port4 {
	status = "okay";
	phy-handle = <&cpsw9g_diob>;
	phy-mode = "qsgmii";
	local-mac-address = [02 60 C8 00 00 03];
	phys = <&cpsw0_phy_gmii_sel 4>;
	phy-names = "mac";
};

/* KONI (XF2) [RTL8211] */
&main_cpsw0_port5 {
	status = "okay";
	phy-handle = <&cpsw9g_koni>;
	phy-mode = "sgmii";
	local-mac-address = [02 60 C8 00 00 04];
	phys = <&cpsw0_phy_gmii_sel 5>;
	phy-names = "mac";
};

/* KLI-OT (XF4) [RTL8211] */
&main_cpsw0_port6 {
	status = "okay";
	phy-handle = <&cpsw9g_kli_ot>;
	phy-mode = "sgmii";
	local-mac-address = [02 60 C8 00 00 05];
	phys = <&cpsw0_phy_gmii_sel 6>;
	phy-names = "mac";
};

/* Profinet 3 (XF8) [RTL8211] */
&main_cpsw0_port7 {
	status = "okay";
	phy-handle = <&cpsw9g_daisy1>;
	phy-mode = "sgmii";
	local-mac-address = [02 60 C8 00 00 06];
	phys = <&cpsw0_phy_gmii_sel 7>;
	phy-names = "mac";
};

/* Profinet 4 (XF9) [RTL8211] */
&main_cpsw0_port8 {
	status = "okay";
	phy-handle = <&cpsw9g_daisy2>;
	phy-mode = "sgmii";
	local-mac-address = [02 60 C8 00 00 07];
	phys = <&cpsw0_phy_gmii_sel 8>;
	phy-names = "mac";
};

&main_cpsw0_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_cpsw9g_mdio_pins_default>;
	bus_freq = <1000000>;
	reset-gpios = <&main_gpio0 10 GPIO_ACTIVE_LOW>;    /* QPHY_RSTn_GPO */
	reset-post-delay-us = <120000>;
	#address-cells = <1>;
	#size-cells = <0>;

	/* KONI (XF2) [RTL8211] */
	cpsw9g_koni: ethernet-phy@1 {
		reg = <1>;
	};

	/* KLI-OT (XF4) [RTL8211] */
	cpsw9g_kli_ot: ethernet-phy@2 {
		reg = <2>;
	};

	/* Unused [YT8614] */
	cpsw9g_phy0: ethernet-phy@8 {
		reg = <8>;
	};

	/* KSI (XF1) [YT8614] */
	cpsw9g_ksi: ethernet-phy@9 {
		reg = <9>;
	};

	/* TP [YT8614] */
	cpsw9g_tp: ethernet-phy@10 {
		reg = <10>;
	};

	/* DIOB [YT8614] */
	cpsw9g_diob: ethernet-phy@11 {
		reg = <11>;
	};

	/* Profinet 3 (XF8) [RTL8211] */
	cpsw9g_daisy1: ethernet-phy@3 {
		reg = <3>;
	};

	/* Profinet 4 (XF9) [RTL8211] */
	cpsw9g_daisy2: ethernet-phy@4 {
		reg = <4>;
	};
};

&usb_serdes_mux {
	idle-states = <1>; /* USB0 to SERDES4 lane 3 */
};

&usbss0 {
	status = "okay";
	pinctrl-0 = <&main_usbss0_pins_default>;
	pinctrl-names = "default";
	ti,vbus-divider;
};

&usb0 {
	status = "okay";
	dr_mode = "host";
	maximum-speed = "super-speed";
	phys = <&serdes4_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

If we remove SerDes 2-3 and 4-2 everything works like charm.

Enabling those two prevents all network communication.

Could you assist us with the configuration, please?

Regards

Daniel

over 1 year ago

0 Siddharth Vadapalli over 1 year ago

TI__Expert 3940 points

Hello Daniel,

Please note that each SERDES instance expects only two sub-nodes within it.
That is because there are two PLLs in the SERDES implying support for up to two different protocols.
As a consequence, it is not possible to have the following configuration:
Lane 0 -> Protocol 1
Lane 1 -> Protocol 1
Lane 2 -> Protocol 2
Lane 3 -> Protocol 1
though the above still has only two protocols.

Thus,
Serdes 2-0 SGMII
Serdes 2-1 SGMII
Serdes 2-2 QSGMII
Serdes 2-3 SGMII
is not a valid configuration, since expressing the above in terms of device-tree sub-nodes will require 3 sub-nodes.

In the case of:
Serdes 4-2 SGMII
Serdes 4-3 USB3
I believe that the changes you have shown above are in addition to including k3-j784s4-main.dtsi and k3-j784s4-evm.dts,
in which case serdes4 node already has a sub-node for DP in k3-j784s4-evm.dts:

&serdes4 {
	serdes4_dp_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <4>;
		#phy-cells = <0>;
		cdns,max-bit-rate = <2700>;
		cdns,phy-type = <PHY_TYPE_DP>;
		resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
			 <&serdes_wiz4 3>, <&serdes_wiz4 4>;
	};
};

Thus, SERDES4 is now being configured for 3 protocols which isn't supported as described above. However, if k3-j784s4-evm.dts is not included, i.e. the sub-node for DP is not present in SERDES4 node, it might be a different issue and I will need more details in that case.

Regards,
Siddharth.

0 Daniel Braunwarth over 1 year ago in reply to Siddharth Vadapalli

Intellectual 360 points

Hi Siddharth

Siddharth Vadapalli said:
Thus,
Serdes 2-0 SGMII
Serdes 2-1 SGMII
Serdes 2-2 QSGMII
Serdes 2-3 SGMII
is not a valid configuration, since expressing the above in terms of device-tree sub-nodes will require 3 sub-nodes.

Understood.

Siddharth Vadapalli said:
believe that the changes you have shown above are in addition to including k3-j784s4-main.dtsi and k3-j784s4-evm.dts,
in which case serdes4 node already has a sub-node for DP in k3-j784s4-evm.dts:

We have defined our own device tree only including k3-j784s4.dtsi so the DP stuff shouldn't be defined.

Siddharth Vadapalli said:
However, if k3-j784s4-evm.dts is not included, i.e. the sub-node for DP is not present in SERDES4 node, it might be a different issue and I will need more details in that case.

Seems like removing the invalid configuration on Serdes 2 resolved the issue with Serdes 4.

Thanks for you help!

Regards

Daniel

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PROCESSOR-SDK-J784S4: SerDes Configuration