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TDA4VM: TDA4VM CPSW9G pc cannot ping MCU2_1

lixiaodong
Prodigy 40 points
Part Number: TDA4VM


Tool/software:

Dear experts,

  I used AutoSar to integrate Eth Virtual Mac on MCU2_1. I used pc to ping MCU2_1, but could not ping, but Cddipc could communicate with MCU2_0 normally. It is based on sdk8.6.

  What is the reason?

MCU2_0 log

I debug based on the development board.

  • 0
    TI__Guru 66500 points

    Hi,

    EthFw will respond for the ARP requests for client IP address on behalf of clients.

    So, AutoSAR client MCU2_1 should register IPv4 with EthFw. If not ARP will not resolve and Ping will not success.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    How do I register  IPv4 with EthFw.What should I do?

  • 0 in reply to lixiaodong
    TI__Guru 66500 points

    Hi,

    We have "Eth_DispatchVirtmacAssociateIPv4Macaddr" API, to register IPV4 with EthFw Server.

    Using the above you can register IP of MCU2_1 client with EthFw.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    The mac address I registered with Ethfw uses the function shown below,Is that not possible?

  • 0 in reply to lixiaodong
    TI__Guru 66500 points

    Hi,

    lixiaodong said:
    The mac address I registered with Ethfw uses the function shown below,Is that not possible?

    Above will register only MAC.

    But for ARP MAC alone not sufficient, we need MAC address + IP Address.

    So, you should have to register IP with EthFW using "Eth_DispatchVirtmacAssociateIPv4Macaddr".

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    I use Eth_DispatchVirtmacAssociateIPv4Macaddr register IP with EthFW, but could not ping.

    MCU2_0 log

    Wireshark log

  • 0 in reply to lixiaodong
    TI__Guru 66500 points

    Hi,

    Usually ARP should continue until to get the response or ping command is running.

    Are you running ping after IP registered with Ethfw right?

    Can you please confirm, will you be able to ping br4 (ethfw) 172.41.1.200? 

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    If we ping br4 (ethfw) 172.41.1.200 before mcu2_1 starts, we can ping it. In addition, we will not ping ethfw when starting this time, but after MCU2_1 registers with EthFW to ping ethfw,Unable to ping ethfw, unable to ping mcu2_1.

  • 0 in reply to lixiaodong
    TI__Guru 66500 points

    Hi,

    Can you please full wireshark log before MCU2_1 and after, i.e. while pinging EthFw in success and fail scenario.
    Also, please share the ALE table before and after.
    Refer to FAQ for collecting ALE table entries.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    I cannot upload file，

    this is ping fail mcu2_0 mcu2_1

    this is ping ok mcu2_0

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Sorry, I don't know how to upload Wireshark log.

    This is the ALE log before mcu2_1 runs.

    Fullscreen ALE_CPSW9G_MCU2_1_befor.txt Download 
    MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: -------CPSWnG ALE TABLE----------------------
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 0 - VLAN INNER 
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_1: GEL Output: IVLAN_ID          = 300
MAIN_Cortex_R5_0_1: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_1: GEL Output: REG_MCAST_FLOOD   = 511
MAIN_Cortex_R5_0_1: GEL Output: FWDUTAG           = 511
MAIN_Cortex_R5_0_1: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_1: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_1: GEL Output: VLAN_MEMBER_LIST  = 511
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 1 - VLAN INNER 
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_1: GEL Output: IVLAN_ID          = 0
MAIN_Cortex_R5_0_1: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_1: GEL Output: REG_MCAST_FLOOD   = 19
MAIN_Cortex_R5_0_1: GEL Output: FWDUTAG           = 19
MAIN_Cortex_R5_0_1: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_1: GEL Output: UNREG_MCAST_FLOOD = 19
MAIN_Cortex_R5_0_1: GEL Output: VLAN_MEMBER_LIST  = 19
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 2 - VLAN INNER 
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_1: GEL Output: IVLAN_ID          = 1
MAIN_Cortex_R5_0_1: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_1: GEL Output: REG_MCAST_FLOOD   = 493
MAIN_Cortex_R5_0_1: GEL Output: FWDUTAG           = 493
MAIN_Cortex_R5_0_1: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_1: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_1: GEL Output: VLAN_MEMBER_LIST  = 493
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 3 - Multicast
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: PORT_MASK        = 0x000001FF
MAIN_Cortex_R5_0_1: GEL Output: SUPER            = 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST IGNORE BITS= 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST_FWD_STATE  = 0
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_1: GEL Output: MULTICAST_ADDR   = 0x0000FFFF 0xFFFFFFFF
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 4 - Unicast
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: TRUNK            = 0
MAIN_Cortex_R5_0_1: GEL Output: PORT_NUMBER      = 0
MAIN_Cortex_R5_0_1: GEL Output: BLOCK            = 0
MAIN_Cortex_R5_0_1: GEL Output: SECURE           = 1
MAIN_Cortex_R5_0_1: GEL Output: TOUCH            = 0
MAIN_Cortex_R5_0_1: GEL Output: AGEABLE          = 0
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_1: GEL Output: UNICAST_ADDR     = 0x000070FF 0x761D92C3
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 6 - Multicast
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: PORT_MASK        = 0x00000001
MAIN_Cortex_R5_0_1: GEL Output: SUPER            = 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST IGNORE BITS= 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST_FWD_STATE  = 0
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_1: GEL Output: MULTICAST_ADDR   = 0x00000180 0xC200000E
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 7 - Multicast
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: PORT_MASK        = 0x00000001
MAIN_Cortex_R5_0_1: GEL Output: SUPER            = 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST IGNORE BITS= 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST_FWD_STATE  = 0
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_1: GEL Output: MULTICAST_ADDR   = 0x0000011B 0x19000000
MAIN_Cortex_R5_0_1: GEL Output: Completed analysis of 1024 ALE entries

    This is the ALE log after mcu2_1 runs.

    Fullscreen ALE_CPSW9G_MCU2_1_after.txt Download 
    MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: -------CPSWnG ALE TABLE----------------------
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 0 - VLAN INNER 
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_1: GEL Output: IVLAN_ID          = 300
MAIN_Cortex_R5_0_1: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_1: GEL Output: REG_MCAST_FLOOD   = 511
MAIN_Cortex_R5_0_1: GEL Output: FWDUTAG           = 511
MAIN_Cortex_R5_0_1: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_1: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_1: GEL Output: VLAN_MEMBER_LIST  = 511
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 1 - VLAN INNER 
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_1: GEL Output: IVLAN_ID          = 0
MAIN_Cortex_R5_0_1: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_1: GEL Output: REG_MCAST_FLOOD   = 19
MAIN_Cortex_R5_0_1: GEL Output: FWDUTAG           = 19
MAIN_Cortex_R5_0_1: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_1: GEL Output: UNREG_MCAST_FLOOD = 19
MAIN_Cortex_R5_0_1: GEL Output: VLAN_MEMBER_LIST  = 19
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 2 - VLAN INNER 
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE        = 2
MAIN_Cortex_R5_0_1: GEL Output: IVLAN_ID          = 1
MAIN_Cortex_R5_0_1: GEL Output: NO FRAG           = 0
MAIN_Cortex_R5_0_1: GEL Output: REG_MCAST_FLOOD   = 493
MAIN_Cortex_R5_0_1: GEL Output: FWDUTAG           = 493
MAIN_Cortex_R5_0_1: GEL Output: LMT NEXT HDR      = 0
MAIN_Cortex_R5_0_1: GEL Output: UNREG_MCAST_FLOOD = 0
MAIN_Cortex_R5_0_1: GEL Output: VLAN_MEMBER_LIST  = 493
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 3 - Multicast
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: PORT_MASK        = 0x000001EC
MAIN_Cortex_R5_0_1: GEL Output: SUPER            = 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST IGNORE BITS= 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST_FWD_STATE  = 0
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_1: GEL Output: MULTICAST_ADDR   = 0x0000FFFF 0xFFFFFFFF
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 4 - Unicast
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: TRUNK            = 0
MAIN_Cortex_R5_0_1: GEL Output: PORT_NUMBER      = 0
MAIN_Cortex_R5_0_1: GEL Output: BLOCK            = 0
MAIN_Cortex_R5_0_1: GEL Output: SECURE           = 1
MAIN_Cortex_R5_0_1: GEL Output: TOUCH            = 0
MAIN_Cortex_R5_0_1: GEL Output: AGEABLE          = 0
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_1: GEL Output: UNICAST_ADDR     = 0x000070FF 0x761D92C3
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 6 - Multicast
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: PORT_MASK        = 0x00000001
MAIN_Cortex_R5_0_1: GEL Output: SUPER            = 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST IGNORE BITS= 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST_FWD_STATE  = 0
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_1: GEL Output: MULTICAST_ADDR   = 0x00000180 0xC200000E
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 7 - Multicast
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: PORT_MASK        = 0x00000001
MAIN_Cortex_R5_0_1: GEL Output: SUPER            = 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST IGNORE BITS= 0
MAIN_Cortex_R5_0_1: GEL Output: MCAST_FWD_STATE  = 0
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_1: GEL Output: MULTICAST_ADDR   = 0x0000011B 0x19000000
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output:  Entry 8 - Unicast
MAIN_Cortex_R5_0_1: GEL Output: ---------------------------------------------
MAIN_Cortex_R5_0_1: GEL Output: TRUNK            = 0
MAIN_Cortex_R5_0_1: GEL Output: PORT_NUMBER      = 0
MAIN_Cortex_R5_0_1: GEL Output: BLOCK            = 0
MAIN_Cortex_R5_0_1: GEL Output: SECURE           = 0
MAIN_Cortex_R5_0_1: GEL Output: TOUCH            = 0
MAIN_Cortex_R5_0_1: GEL Output: AGEABLE          = 0
MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE       = 1
MAIN_Cortex_R5_0_1: GEL Output: UNICAST_ADDR     = 0x000070FF 0x761D92C4
MAIN_Cortex_R5_0_1: GEL Output: Completed analysis of 1024 ALE entries

  • 0 in reply to lixiaodong
    TI__Guru 66500 points

    Hi, 

    Will be OoO, will check on Wednesday and get back you. Kindly wait till then. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Problem has been solved now and and I can now ping MCU2_1, but now I have a question why use Eth_DispatchVirtmacAddMcastAddr add broadcast address to  Ethfw leads to can't ping MCU2_1? 

    EthVirtmacApp_addMcastAddr(BcastAddr, FALSE);

static void EthVirtmacApp_addMcastAddr(uint8 *macAddr, boolean addHostPort)
{
    Std_ReturnType status;
    Eth_PortListType portList;

    portList.numPorts = 0;
#if defined (SOC_J721E)
    portList.numPorts += 6;
    portList.ports[0] = ETH_PORT_MAC_PORT_2;
    portList.ports[1] = ETH_PORT_MAC_PORT_3;
    portList.ports[2] = ETH_PORT_MAC_PORT_5;
    portList.ports[3] = ETH_PORT_MAC_PORT_6;
    portList.ports[4] = ETH_PORT_MAC_PORT_7;
    portList.ports[5] = ETH_PORT_MAC_PORT_8;
#elif defined (SOC_J784S4)
    portList.numPorts += 2;
    portList.ports[0] = ETH_PORT_MAC_PORT_3;
    portList.ports[1] = ETH_PORT_MAC_PORT_5;
#else
    portList.numPorts += 2;
    portList.ports[0] = ETH_PORT_MAC_PORT_2;
    portList.ports[1] = ETH_PORT_MAC_PORT_3;
#endif

    if (addHostPort)
    {
       portList.ports[portList.numPorts] = ETH_PORT_HOST_PORT;
        portList.numPorts++;
    }
    expectedSid = ETH_SID_DISPATCH_VIRTMAC_ADD_MCAST_MACADDR;
    status = Eth_DispatchVirtmacAddMcastAddr(0, macAddr, 0, 0, &portList);
    ETHAPP_BUSY_WAIT();
}

    I refer to sdk8.6 eth_virtmac_app demo logic.

  • 0 in reply to lixiaodong
    TI__Guru 66500 points

    Hi,

    lixiaodong said:
    but now I have a question why use Eth_DispatchVirtmacAddMcastAddr add broadcast address to  Ethfw leads to can't ping MCU2_1? 

    Here, client is overwriting the ALE Broadcast entry written by EthFw and removed Host Port & MAC Only Ports from PortMask.
    So, these ports will not receive the Broadcast packets.

    It was fixed in latest SDK release. Client is not adding any Broadcast entries.
    Also, it is example test application reference to customer from TI for validation of MCAL Eth Driver.

    Best  Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 40 points

    Thanks for your support, this issue is resolved.