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AM623: DDR4 Board Design and Layout Guidance

MASAKI OOTAKA
Prodigy 180 points

Part Number: AM623

Tool/software:

Application Note "AM62x DDR Board Design and Layout Guidelines" includes a description of Routing Limits for "2.16.2 CK and ADDR_CTRL Routing Limits".
There is also a limitation on "Vias per trace", please let me confirm the following two issues.
(1) Does this limit include the number of vias when using BGA Pad-on vias?
(2) If the number of vias exceeds this limit, is it acceptable to exceed the limit if it is confirmed that there is no problem by SI analysis of regarding of DDR4?

  • +1
    TI__Guru* 96081 points

    1. Yes via-in-pad still applies, as it still introduces a discontinuity in the trace which need to be minimized

    2. Yes, this is reflected in note 1 below the table.  If proper signal integrity analysis is perform and reveals good margins, the number of via can exceed this limit.

    Regards,

    James