J784S4XEVM: C7x GPIO Interrupt issue

Hi Burak,

Our expert is currently out of office; please expect a 3-4 day delay in response.

Best,
Jared

Hi Burak,

Thank you for patience. Can you provide your code where you setup the GPIO instance and interrupt?
Thanks,

Neehar

Sure. Here is the GPIO related code pieces in my application.

//The lines below are located under GPIO_board.c file similar to the GPIO example of J784S4.

#define MAIN_GPIO_ID_0 0
#define MAIN_GPIO_PIN_NUM_1 11

#define PADCONFIG_11 0x0011C02C

GPIO_PinConfig gpioPinConfigs[] =
{
  GPIO_DEVICE_CONFIG(MAIN_GPIO_ID_0, MAIN_GPIO_PIN_NUM_1) |
  GPIO_CFG_IN_INT_BOTH_EDGES | GPIO_CFG_INPUT
}

GPIO_CallbackFxn gpioCallbackFunctions[] =
{
  NULL
}

GPIO_v0_Config GPIO_v0_config =
{
  gpioPinConfigs,
  gpioCallbackFunctions,
  sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
  sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
  0x8U
#else
#if defined(BUILD_C7X)
  0x01U
#else
  0x20U
#endif
#endif
}

//In main, where I setup the GPIO instance,

int main()
{
...

Board_initCfg boardCfg;
boardCfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO;
Board_init(boardCfg);

//set SoC init configuration
GPIO_v0_HwAttrs gpio_cfg;
GPIO_socGetInitCfg(MAIN_GPIO_ID_0, &gpio_cfg);
gpio_cfg.baseAddr = CSL_GPIO0_BASE;
gpio_cfg.intCfg[gpioPinNums[MAIN_GPIO_ID_0]].intcMuxNum = INVALID_INTC_MUX_NUM;
gpio_cfg.intCfg[gpioPinNums[MAIN_GPIO_ID_0]].intcMuxInEvent = 0;
gpio_cfg.intCfg[gpioPinNums[MAIN_GPIO_ID_0]].intcMuxOutEvent = 0;
GPIO_socSetInitCfg(MAIN_GPIO_ID_0, &gpio_cfg);

OS_init();

//set callback and enable
GPIO_init();
GPIO_setCallback(MAIN_GPIO_ID_0, someCallbackFxn);
GPIO_enableInt(MAIN_GPIO_ID_0);

//set padconfig register
Board_init(BOARD_INIT_UNLOCK_MMR);
*((uint32_t *)(PADCONFIG_11)) = 0x00240007;

...

}

Thanks.

Hi Burak,

The GPIO initialization you have looks correct.

If you are using No Boot mode, are you using the GEL scripts to initialize and boot all the cores?
Thanks,

Neehar

Hi,

I follow the SDK documentation. As indicated in CCS setup for J784S4 section (section 7), I have set the initialization script "J7AHP.gel" located under CCS installation path for SMS_TIFSM (CORTEX M4F 0)  and run launch.js script under <ti/drv/sciclient/tools/ccsLoadDmsc/j784s4> before debugging.

After running the script, MCU_Cortex_R5_0 is loaded with SYSFW and ready to run, I connect to C71x_0 and load my program. I first run the SYSFW and then the C71x program.

Should I also set an initialization script specifically for C7x1_0 core under Target Configuration "Advanced" tab as we do for SMS_TIFSM?

Hi Burak,

Burak Burak said:

Should I also set an initialization script specifically for C7x1_0 core under Target Configuration "Advanced" tab as we do for SMS_TIFSM?

No, you should not have to. You should be able to simply connect to C71x_0 and load the program.

Let me look into this further and get back to you.
Thanks,
Neehar

Hi Burak,

Which cores have you tested on and how are you building your application?

Currently, you cannot build the GPIO example within the PDK as it does not have support to be built for C7x cores.
Thanks,

Neehar

Hi Neehar, would that create any difference in terms of how the example works?

Burak Burak said:

*((uint32_t *)(PADCONFIG_11)) = 0x00240007;

Whşch  register flag odes 0x00200000 correspond to? In the original example it is 0.

Hi Neehar,

I am not directly using the example application coming with the PDK. I have reviewed and modified it to get interrupts from SW3 switch on the board. I tried the same application on an ARM R5F core and it worked without any problem, but still having the issue with C7x cores. Predefined symbols in the project properties are set correctly for the target core.

Hi Ozan,

Ozan Akyildiz said:

Hi Neehar, would that create any difference in terms of how the example works?

There may be issues as the example may not be able to fully build for C7x cores.

Ozan Akyildiz said:

Whşch  register flag odes 0x00200000 correspond to? In the original example it is 0.

Setting padconfig register to 0x00200000 will solely disable TX driver and set Mux mode to 0.

Hi Burak,

Can you also provide your code for the GPIO_socConfigIntrPath() API call?

Thanks,

Neehar

Burak Burak said:

In GPIO_socConfigIntrPath function located in <ti/drv/gpio/soc/j784s4/GPIO_soc.c>

retVal = GPIO_socGetIrqRange(ir_id, dst_id, &irq_range_start, &irq_range_num);

returns -1. When I debug it, I observe that,

        retVal = Sciclient_rmGetResourceRange(
                &req,
                &res,
                SCICLIENT_SERVICE_WAIT_FOREVER);

Hi Neehar Sawant

As indicated in the question, it is located in that given path in the PDK. GPIO_init() function initiates GPIO_setConfig_v0() function located in <ti/drv/gpio/src/v0/GPIO_v0.c> which also calls GPIO_socConfigIntrPath() under the hood.

Actually I didn't touch the makefile, so I am building for R5 cores (mcu2_0 specifically)

Hi Burak,

What are the ir_id and dst_id values that are used to call GPIO_socGetIrqRange()?

Hi Ozan,

Ozan Akyildiz said:

Actually I didn't touch the makefile, so I am building for R5 cores (mcu2_0 specifically)

You should not have any issues building for R5 cores of MCU2_0. If you do, you can create another thread specifying the issues you have and we can assist you.
Thanks,

Neehar

Hi Neehar,

ir_id  = 10 which is TISCI_DEV_GPIOMUX_INTRT0

dst_id = 44 that is TISCI_DEV_COMPUTE_CLUSTER0_CLEC

GPIO_socGetIrqRange returns -1 with irq_range_start = 757 and irq_range_num = 17450.

Thanks.

Hi  Neehar Sawant,

Is there an update?

Hi Neehar,

I have modified the sciclient_defaultBoardcfg_rm.c file such that, .resasg_entries is partitioned for .host_id = TISCI_HOST_ID_C7x_0_0 and TISCI_HOST_ID_C7x_0_1 starting from the resource = 40 until 44 as num_resource = 2 for each. These 4 resources are taken from TISCI_HOST_ID_A72_2 starting from 32. Then, I rebuilt sciclient_ccs_init and sciserver_testapp_freertos and replaced the output artifacts with the binaries located under launch.js location. GPIO_socGetIrqRange still returns -1 with irq_range_start = 215 (in this case) and irq_range_num = 17450.

Could you please specifically indicate the process to rebuild the board configuration so that I cannot miss any steps?

Hi Neehar,

Thank you for your reply. I have followed the given documents. GPIO_socGetIrqRange() successfully returned with irq_range_start = 444 and irq_range_num = 4. I have traced the whole GPIO_setConfig_v0 function and nothing returned false. However, I am still unable to getting interrupts.

In SysConfig tool, I have only added C7x_0_0 which is disabled by default and modified the "Main GPIO interrupt router count" with 4 under Interrupt Routers section. The screenshot is in the attachment. Then, using the generated sciclient_defaultBoardcfg_rm.c file, I have rebuilt the sciclient.

It generated object files for PDK libraries and the executables for "sciclient_ccs_init" and "sciserver_testapp_freertos" applications. I have only replaced the binaries that are loaded with the execution of launch.js script:

• sciclient_ccs_init_mcu1_0_release.xer5f
• sciserver_testapp_freertos_mcu1_0_release.rprc
• sciserver_testapp_freertos_mcu1_0_release.xer5f

Is it misconfigured in SysConfig tool?

Note: I have also assigned 4 Main GPIO interrupt router count for C7X_0_1. It is not shown in the screenshot.

Hi Burak,

Burak Burak said:

However, I am still unable to getting interrupts.

When you say you are unable to get interrupts do you mean the callback function is not reached?

Did you use the boardcfg_update.sh script or did you do it manually?

Can you send your sciclient_defaultBoardcfg_rm.c file for me to look into?

Thanks,

Neehar

Hi Neehar,

Yes, callback function is not triggered. I have used boardcfg_update.sh script as suggested.

cd <PDK_PATH>/packages/ti/drv/sciclient/tools
./boardcfg_update.sh j784s4_evm --boardcfg=path/to/generated/j721e/sciclient/defaultBoardcfg/rm/c/file

I am currently out of office. I will provide the generated sciclient_defaultBoardcfg_rm.c file as soon as possible.

Hi Burak,

Great thank you!

Thanks,

Neehar

Hi Neehar,

Here is the sciclient_defaultBoardcfg_rm.c file.

Thank you.sciclient_defaultBoardcfg_rm.zip

Hi Neehar Sawant

Did you have any chance to have a look at it?

Thanks.

Hi Burak,

Thanks for this information. 

You will have to also ensure the interrupt is registered on the C7x side using Osal. This can be double checked with the CLEC registers and to ensure interrupts are enabled.

Additionally, are you using line or banked interrupts?

Thanks,

Neehar

Hi Neehar,

Thank you for the response.

What you mentioned about interrupt registration on C7x using OSAL lib is basically done in GPIO_setConfig_v0 function. You may check the screenshot, register values are there. Note that hwiHandle return with a valid address and it seems to be successful.

CSL_GPIO0_BASE is used as base address so it is banked interrupt if I am not wrong. I don' t get actually what you mean by line and banked interrupts.

Neehar Sawant said:

This can be double checked with the CLEC registers and to ensure interrupts are enabled.

How can I get this information?

Hi Burak,

You may want to check the below registers:

Thanks,

Neehar

Hi Neehar,

Does it belong to J784S4 TRM? It shows C66 subsystem which is not available in J784S4.

Hi Burak,

Sorry for the confusion. This image was taken from the J721E TRM. There should be a similar register for J784S4 you can access.
Thanks,

Neehar

Hi Neehar Sawant

It is not in TRM but I found it in the xls file where registers are listed.

As shown in the screenshot, I have checked the 0xA00004 address since I am trying to register the interrupt number 0 (no need to add offset). I have checked after GPIO_init() and GPIO_enableInt() calls but the value at 0xA00004 is 0 meaning that interrupt output is not enabled since bit-16 is zero. By the way, I have checked the value at 0xA00000 and it is the default value 0x66948100 as depicted in the screenshot.

Hi Burak,

Can you test adjusting bit 16 of the register and test if you are able to get an interrupt?

Thanks,

Neehar

Hi Neeahar,

I have manually set it to 1 but it didn' t work.

Hi Burak,

Sorry for the delayed response as I was out of office. Can you send me the value of the register?

Thanks,

Neehar

Hi Neehar,

Reg @ 0xA00000 = 0x66948100
Reg @ 0xA00004 = 0x00000000

Thanks.

Hi Neehar Sawant

Is there any update?

Hi Burak,

Burak Burak said:

Reg @ 0xA00004 = 0x00000000

Where are you reading this value from? Are you able to read the registers from CCS?

I believe you may have to read a different register as the values will be at the address depending on which output is used from the mux router. The address will be 00A0 0004h+ (j * 4h); where j = 0 to 63d.

However, only these are routed to the CLEC:

Thanks,

Neehar

Hi Burak,

Is this issue still open?

Thanks,

Neehar

Hi,

Yes, the issue is still open. I am reading the register value by creating an expression at that memory address.

From the list you provided, I understand that I can' t create a GPIO instance by using index = 0 for C7x as it is not routed to the CLEC. Thus, I have tried creating it by index 8, but, unfortunately, nothing has changed.

Hello, 

Our expert is out of office. Please expect a delay in response.

Thanks,
Sarabesh S.

Hi Burak,

Can you test with using one of the indices 32-35? Based on the previous Boardcfg_rm file you provided before, these indices should be allocated from C7x from the GPIOMUX_INTRTR. Additionally, can you provide the register data for the index you choose?

Thanks,

Neehar

Hi Burak,

Following up, is this issue still open?

Thanks,

Neehar