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C6A8168: DDR 3 Configuration

KENJI SASAKI
Prodigy 70 points

Hi,

I have a question about the restrictions that applies to DDR3 device configuration.

We have designed the memory configuration  of our system, as per your TRM, as follows:

  EMIF0-CS0: 2Gb(x16) x 2 parallel connection, 32bit access
  EMIF0-CS1: 2Gb(x16) x 2 parallel connection, 32bit access
  EMIF1-CS0: 2Gb(x16) x 2 parallel connection, 32bit access
  EMIF1-CS1: 2Gb(x16) x 2 parallel connection, 32bit access

Although we tweeked with  whatever parameters available based on the actual line length, i.e. delay ratio, ODT, drive & slew rate, we were not able to obtain any stable parameter from the software leveling process.

My question boils down to the following:

#1 Is cascaded memory configuration using CS1 technically feasible? If not, what is the workaround?
#2 Is Dynamic ODT functioning correctly? If not, what is the workaround.

Thanks for your kind attention and support (we are pretty desperate...)

Best regards,

Ken

  • 0
    TI__Mastermind 25055 points

    Hello,

    I apologize for any confusion here. The DDR connection block diagrams in the TRM were intended only as a generic reference, and above them it states that one must refer to the device-specific datasheet for details of supported configurations and topologies.  We will remove these block diagrams from the TRM to avoid future confusion.

    The type of arrangement suggested above might theoretically work, but this device does not support the configuration.  Only the configurations shown in the datasheet are supported.  Using 4 8-bit devices is supported and should cost less.

    The big issue with the suggested arrangement is the bifurcation of the data lines.  We don't think they would run at speed because of the additional delay due to the split traces.  Dual rank DDR3 interfaces assume the DDR devices are mirrored on the board with a very short trace connecting the data lines together (less than 0.25 inches).

    We are only supporting the use of one CS (DDRx_CS[0]) because a second CS is not needed to fully populate the memory space available in the device memory map for DDR3.

    Regards,
    Marc