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C6678 Power - Fusion file for the "1off UCD9222 / 2off UCD7242 / 2off DSP's / 20A each" design

Other Parts Discussed in Thread: UCD9222, UCD7242, UCD74111, UCD74106

Hi

 

Apologies for the number of posts on this matter, but the power requirements for C6678 are very complicated and I want to make sure and get them right.

 

Having checked out the power estimation spreadsheet, it now seems that CVDD needs in excess of 15A, for a 1.25GHz part.  Page 54 of the Keystone Hardware Design Guide shows an example ("1off UCD9222 / 2off UCD7242 / 2off DSP's / 20A each") of how to generate this for two DSP's.

 

I would very much like a copy of the Fusion Digital Power Designer file for this configuration.  Can you please post it to this forum?  Without it I expect to spend many hours in the depths of Fusion and am not sure I know enough to do it competently.

 

Cheers,

 

Richard

  • I have noticed that there is an error in the schematics for the reference design "1off UCD9222 / 2off UCD7242/ 2off DSP's / 20A each" on page 53 of Keystone Hardware Design Guide.

    On device U4, pin 1 (PWM-B) connects to pin 25 (SRE-A).  I think it should connect to pin 26 (PWM-A).

    Are you aware of any other changes/fixes to the schematics for this example, as I'm copying them for my design.

     

    regards,

    Richard

  • I think I have noticed another error in the schematics on page 54 of the HW Design guide.

    R29 connects signal "EAn2" to PGND (U3 pins 15, 16, 17), but it also incorrectly connects to pin 2 of L1.  This effectively shorts the power rail to GND!

     

    Richard

  • Hi Richard,

     

    For your observation on the current requirement for the AVS supply, you should be seeing under 15A unless you are really stressing the device. Probably you are already, but please refer to the appnote for information on the utilization settings -- http://www.ti.com/lit/pdf/SPRABI5.

    If you open the spreadsheet and toggle the power/current view you will see 13.5A on the AVS. Widening the DDR and adding some CPU load and some of the unused peripherals still keeps this under 15 unless you are really loading.  One comment, in particular, is on the CPU utilization. The %SP cell is one that you should not try to overload. It is a percentage of the full datapath utilization, where 100% would mean all 8 functional units active every cycle with no stalls. The 27% that is in the spreadsheet by default (at the time of this post) is a fairly high steady-state utilization.

    To analyze your own software, it is possible to get a detailed profile of the parallelism of key functions within the CCS simulator, and a function profile (%time in critical functions) on your hardware with the emulator.

     

    For your comments on the design guide, we will take a look and ensure that the schematics are up to date. Thank you for highlighting!

     

    Best regards,

    Dave

     

  • Hi Dave,

     

    You are right I should have really said 13 Amps for CVDD.  However this still puts me firmly in the >10A scenario.  So I have to join both halves of the UCD7242 together to provide the 13Amps.  So the example on page 54 of the Keystone Hardware Design Guide still applies - ("1off UCD9222 / 2off UCD7242/ 2off DSP's / 20A each").

     

    My question was a request for the Fusion Digital Power Designer file for this configuration.  Can you please post it to this forum?  

     

    regards,

     

    Richard

  • Richard,

    The C6678 device can be configured to perform the functions of a Media Gateway operating at 1000MHz with an 85C max case temperature where the CVDD current remains below 10A.  The recommended CVDD power solution for this application is the UCD9222 with half of the UCD7242.  Alternately, the UCD74106 is a single-channel power stage device that can be used.  Higher performance applications where the DSP operates at 1000MHz with a 100C max case temperature or 1250MHz with an 85C max case temperature will have a CVDD current around 12A or 13A.  The recommended CVDD power stage for these applications is the UCD74110/UCD74111 which can supply up to 15A.  The C6678 and C6670 EVM designs contain these devices.  Please refer to the EVM designs on the web page of our contract manufacturer, Advantech, at http://www.advantech.com/Support/TI-EVM/.  This web site also contains the Fusion Digital Power Designer configuration files for these implementations.

    The Fusion Digital Power Designer software and documentation can be downloaded from the following page on TI.COM: http://www.ti.com/tool/fusion_digital_power_designer.  Even though we provide the configuration files for the EVM, designers must become familiar with the proper use of the Fusion Digital Power Designer software.  The control loop behavior will change as the exact parts in the power stage vary.  The inductor and capacitors chosen must be properly modeled in the GUI for the power supply to work at the optimum performance level desired.

    Tom

     

  • Richard,

    There are other solutions available that can be coupled with these digital controllers.  Please refer to the Power Management Guide:  http://www.ti.com/litv/pdf/slvt145k on page 32.  It shows the Power Stage FET Driver devices mentioned above as well as others.  It also shows the complete Power Train solutions which include the inductor and bulk capacitance.  These can be used to simplify your design and help you keep it constrained to a small footprint.

    Tom

     

  • I have an update on the availability of the UCD74110 and UCD74111 devices.  The UCD74110 has been ramped to full production status.  The datasheet has been updated and formally states Vin operation up to 10V.  The enhanced device that supports 12V and beyond at 15A is the UCD74111.  Its design is progressing.  Initial customer samples will be available in January with full qualification and production release planned for April.  Please request samples through you FAE if you wish to receive early samples.

    Tom