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TDA4VM: Edgeai: Topk custom layer implementation review required from quantization perspective

Part Number: TDA4VM

Tool/software:

Hello,

We are trying to run out model on EdgeAI 9.20.07 https://github.com/TexasInstruments/edgeai-tidl-tools/tree/09_02_07_00?tab=readme-ov-file.

It has TopK, So out team came up with the implementation in the attached files. Other changes required in the SDK9.2 we are able to make and build and are able to run for fp32, i.e. tensor_bits 32. Also our model works fine without C7x offload (running with -d option). We are currently having problems running int16 i.e tensor_bits 16. The Topk output is correct when the values are checked inside the function. The following Data Convert layer mutates the values and the final output is incorrect.

Since two output buffers are not supported yet in SDK9.2, we are just passing the 'indexes' for now. Since, the 'indexes' output is independent of the input type and quantization parameters, the following Data Convert should not apply those parameters.

Please help review the attached implementation and let us know the changes required for int16 execution.

tidl_topK.h

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/**
 *  \file tidl_topK.c
 *
 *  \brief This file defines kernel functions for TopK layer
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include "tidl_alg_int.h"
#include "tidl_commonUtils.h"
#include "tidl_topK.h"
#include "math.h"
#include <limits>

//#define TIDL_REF_BATCH_NORM_DEBUG
/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                  Internal/Private Function Declarations                    */
/* ========================================================================== */

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

/* ========================================================================== */
/*                       Static Function Definitions                          */
/* ========================================================================== */


template <class Tin, class Tout0, class Tout1>
static void TIDL_refTopK_new(sTIDL_Network_t *net,
                                      Tin *pIn,
                                      int32_t length,
                                      int32_t k,
                                      Tout0 *pOut0,
                                      Tout1 *pOut1,
                                      const sTIDL_Layer_t *tidlLayer)
{
  Tin value;
  Tin *inData = (Tin *)pIn;
  Tout0 *outData0 = (Tout0 *)pOut0;
  Tout1 *outData1 = (Tout1 *)pOut1;
  int32_t x1, x2, x3;

  for(x1 = 0; x1 < k; x1++)
  {
    outData0[x1] = (Tout0)0;
  }

  for(x1 = 0; x1 < k; x1++)
  {
    outData1[x1] = std::numeric_limits<Tout1>::lowest();
  }

  for(x1 = 0; x1 < length; x1++)
  {
    value = inData[x1];
    for(x2 = 0; x2 < k; x2++)
    {
      if(value > (Tin)(outData1[x2]))
      {
        for(x3 = k - 1; x3 >= x2 + 1; x3--)
        {
          outData0[x3] = outData0[x3 - 1];
          outData1[x3] = outData1[x3 - 1];
        }
        outData0[x2] = (Tout0)x1;
        outData1[x2] = (Tout1)value;
        std::cout << "Inside TopK: index-" << outData0[x2] << ", value-" << outData1[x2] << std::endl;
        break;
      }
    }
  }
  
  
}


static int32_t TIDL_refTopKProcess(TIDL_NetworkCommonParams *commonParams,
                                        sTIDL_AlgLayer_t *algLayer,
                                        const sTIDL_Layer_t    *tidlLayer,
                                        sTIDL_TopKParams_t *params,
                                        void *inPtr,
                                        void *outPtr0,
                                        void *outPtr1,
                                        const sTIDL_DataParams_t *inDataParams,
                                        const sTIDL_DataParams_t *outDataParams)
{
  int32_t status = TIDL_SUCCESS;
  int32_t k = params->k;
    if (inDataParams->elementType == TIDL_SinglePrecFloat)
    {
        TIDL_refTopK_new(commonParams->createParams->net,
              (float32_tidl*)inPtr, 
              inDataParams->dimValues[TIDL_DIM_WIDTH],
              k,
              (float32_tidl*)outPtr0,
              (float32_tidl*)(((float32_tidl*)outPtr0) + (k)),
              tidlLayer
              );
    }
    else if (inDataParams->elementType == TIDL_UnsignedShort)
    {
        TIDL_refTopK_new(commonParams->createParams->net,
              (uint16_t*)inPtr, 
              inDataParams->dimValues[TIDL_DIM_WIDTH],
              k,
              (uint16_t*)outPtr0,
              (uint16_t*)(((uint16_t*)outPtr0) + (k)),
              tidlLayer
              );
    }
    else if (inDataParams->elementType == TIDL_SignedShort)
    {
        TIDL_refTopK_new(commonParams->createParams->net,
              (int16_t*)inPtr, 
              inDataParams->dimValues[TIDL_DIM_WIDTH],
              k,
              (int16_t*)outPtr0,
              (int16_t*)(((int16_t*)outPtr0) + (k)),
              tidlLayer
              );
    }
    else if (inDataParams->elementType == TIDL_UnsignedChar)
    {
        TIDL_refTopK_new(commonParams->createParams->net,
              (uint8_t*)inPtr, 
              inDataParams->dimValues[TIDL_DIM_WIDTH],
              k,
              (uint8_t*)outPtr0,
              (uint8_t*)(((uint8_t*)outPtr0) + (k)),
              tidlLayer
              );
    }
    else if (inDataParams->elementType == TIDL_SignedChar)
    {
        TIDL_refTopK_new(commonParams->createParams->net,
              (int8_t*)inPtr, 
              inDataParams->dimValues[TIDL_DIM_WIDTH],
              k,
              (int8_t*)outPtr0,
              (int8_t*)(((int8_t*)outPtr0) + (k)),
              tidlLayer
              );
    }

  return status;
}

int32_t TIDL_topKProcess(TIDL_NetworkCommonParams          *commonParams,
                              sTIDL_AlgLayer_t     *algLayer,
                              sTIDL_Layer_t        *tidlLayer,
                              void                 *inPtrs[],
                              void                 *outPtrs[],
                              int32_t layerIdx)
{
  int32_t  status      = TIDL_SUCCESS;
  uint8_t  (*inPtr)     = (uint8_t (*))(inPtrs[0]);
  int8_t   (*outPtr0)   = (int8_t (*))(outPtrs[0]);
  int8_t   (*outPtr1)   = (int8_t (*))(outPtrs[1]);
  printf("\n****** in TOPK ***********\n");

  
  sTIDL_TopKParams_t *params = &tidlLayer->layerParams.topKParams;


    sTIDL_DataParams_t        *inDataParams;
    
    inDataParams = TIDL_getDataParams(commonParams->createParams->net, tidlLayer->inData[0]); 

      
      status = TIDL_refTopKProcess(commonParams,
                                        algLayer,
                                        tidlLayer,
                                        params,
                                        inPtr,
                                        outPtr0,
                                        outPtr1,
                                        inDataParams,
                                        &tidlLayer->outData);  
                                        
      //print values
      printf("debug_TopK_output: k-%d, eltType-%d\n", params->k, tidlLayer->outData.elementType);
      if(tidlLayer->outData.elementType == TIDL_SinglePrecFloat) {
        float *tst = (float *)(outPtr0);
        printf("indexes - ");
        for (int i = 0; i < params->k; i++)
        {
          printf("%f ", tst[i]);
        }
        printf("\nvalues - ");
        float *gst = (float *)(&(tst[params->k]));
        for (int i = 0; i < params->k; i++)
        {
          printf("%f ", gst[i]);
        }
        printf("\n");
      }
      else if (tidlLayer->outData.elementType == TIDL_UnsignedShort) {
        uint16_t *tst = (uint16_t *)(outPtr0);
        printf("indexes - ");
        for (int i = 0; i < params->k; i++)
        {
          printf("%d ", tst[i]);
        }
        printf("\nvalues - ");
        uint16_t *gst = (uint16_t *)(&(tst[params->k]));
        for (int i = 0; i < params->k; i++)
        {
          printf("%d ", gst[i]);
        }
        printf("\n");
      }
      else if (tidlLayer->outData.elementType == TIDL_SignedShort) {
        int16_t *tst = (int16_t *)(outPtr0);
        printf("indexes - ");
        for (int i = 0; i < params->k; i++)
        {
          printf("%d ", tst[i]);
        }
        printf("\nvalues - ");
        int16_t *gst = (int16_t *)(&(tst[params->k]));
        for (int i = 0; i < params->k; i++)
        {
          printf("%d ", gst[i]);
        }
        printf("\n");
      }
      else if (tidlLayer->outData.elementType == TIDL_UnsignedChar) {
        uint8_t *tst = (uint8_t *)(outPtr0);
        printf("indexes - ");
        for (int i = 0; i < params->k; i++)
        {
          printf("%d ", tst[i]);
        }
        printf("\nvalues - ");
        uint8_t *gst = (uint8_t *)(&(tst[params->k]));
        for (int i = 0; i < params->k; i++)
        {
          printf("%d ", gst[i]);
        }
        printf("\n");
      }
      else if (tidlLayer->outData.elementType == TIDL_SignedChar) {
        int8_t *tst = (int8_t *)(outPtr0);
        printf("indexes - ");
        for (int i = 0; i < params->k; i++)
        {
          printf("%d ", tst[i]);
        }
        printf("\nvalues - ");
        int8_t *gst = (int8_t *)(&(tst[params->k]));
        for (int i = 0; i < params->k; i++)
        {
          printf("%d ", gst[i]);
        }
        printf("\n");
      }


  commonParams->createParams->net->TIDLLayers[layerIdx].outData.tensorScale = 1.0f;
  if((commonParams->createParams->flowCtrl & TIDL_FLOW_CTRL_REF_STAT) == TIDL_FLOW_CTRL_REF_STAT)
  {
    TIDL_Obj intAlgObj;
    TIDL_CreateParams createParams;

    memcpy(&createParams, commonParams->createParams, sizeof(TIDL_CreateParams));
    intAlgObj.createParams = (TIDL_CreateParams *) &createParams;
    TIDL_UpdateScaleFactors(&intAlgObj, layerIdx, 0, 0, 1);
  }
  TIDL_enableL1DandL2CacheWb();
    
  return status;
}

log_e2e_int16_c.txtlog_e2e_int16_run.txt

  • Hello,

    Please try to provide some support for the above review, Although, I was able to implement workaround in SDK9.2 for the above issue.

    Now, the current issue is with persim.

    By applying below changes, we are able to disable the perfsim tool in case of edgeAI for tensorbits=16. And getting expected results for our model. 

    Change1--> 
    int32_t tidl_setParamsForPostProcessNet(int32_t tensor_bits)
    {
      //add below lines in the function
      gParams.numParamBits = tensor_bits;
      gParams.numFeatureBits = tensor_bits;
      printf("*****executeNetworkCompiler : Disabled - tidl_setParamsForPostProcessNet\n");
      gParams.executeNetworkCompiler = 0;
    }
     
    Change2 --> void setDefaultParams(tidl_import_config * params)
    {
      //add below lines in the function
      params->executeNetworkCompiler = 0;
      printf("*****executeNetworkCompiler : Disabled\n");
    }
    ====================
    With above changes perfsim can be disabled. 
    

    But after re-enabling the perfsim tool, I am not getting expected results.

    Some layer in between is returning all zeros. When i try to compare the traces (i.e. perfsim enabled vs disabled), i see that the layers are rearranged by perfsim. Logs with perfsim disbled and enabled are attached below.

    log_4_fnc_segv2_1_without_perfsim.txt.

    log_4_fnc_segv2_1_with_perfsim.txt

    To make the model inference run on tda4x, Is Perfm Sim enabling is required ???? 

     

    Below are our observations with perfsim on target --> 

    1. On Target, with PerfSim enabled we are seeing segmentation fault.
    2. With perfsim disabled we are seeing the error TIDL_E_DATAFLOW_INFO_NULL
  • Hi,

    On Target, with PerfSim enabled we are seeing segmentation fault.

    From the logs I am not seeing any segfault, I see that multiple iterations finished, can you help to locate where segmentation fault is happening?

    With perfsim disabled we are seeing the error TIDL_E_DATAFLOW_INFO_NULL

    For target execution perfsim cannot be disabled, so this error is expected if you disable perfsim.

    Regards,

    Anshu

  • HI Anshu,

    The logs are from PC execution.

    I was able to modify our graph and get the first iteration of perfsim to work. The second iteration of perfsim fails with the following error.

    ------------------ Network Compiler Traces -----------------------------
    successful Memory allocation
    successful Workload Creation
    Rerunning network compiler

    ------------------ Network Compiler Traces -----------------------------
    Invalid  layer parameters for layer 135, 29
    Error : Error Code = <ERR_UNKNOWN>
    Segmentation fault (core dumped)

    4_fnc_int16.txt

    I was able to check by putting nodes in deny list that the error is caused either by Topk or nodes close to Topk layer.

  • Hi Anshu,

    For the second iteration of perfsim, which runs after the function TIDL_removeDCLayersfromPCNet, I could further make changes in the SDK9.2 i.e. disabled the mergereshapeLayers function in the TIDL_removeDCLayersfromPCNet.

    Now perfsim is running fine, with the following logs. Please let me know if disabling mergereshapeLayers is fine or not.

    ----------------- Network Compiler Traces -----------------------------
    successful Memory allocation
    successful Workload Creation
    Rerunning network compiler

     

    ------------------ Network Compiler Traces -----------------------------
    successful Memory allocation
    successful Workload Creation

    Further, when we tried running on target. We are getting error, VX_ZONE_ERROR:[tivxKernelTIDLCreate:910] Network version - 0x00000000. I have raised separate ticket for the target issue.

    e2e.ti.com/.../tda4vm-edgeai-vx_zone_error-tivxkerneltidlcreate-910-network-version---0x00000000-observed-on-target

  • Hi Deepanshu,

         Can you run the following script on target before running your application and share the logs ( also make sure to set debugTraceLevel = 2) : 

    source /opt/vision_apps/vision_apps_init.sh


    Regards,

    Anshu

  • Hello,

    PFA the logs.

    root@j721e-evm:~/test_lanedetect/edgeai-tidl-tools/examples/osrt_python/ort# python3 onnxrt_ep_fnc_safety_fp32.py                                                             
    Available execution providers :  ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider']
    
    Running 1 Models - ['fnc_safety_fp32']
    
    
    Running_Model :  fnc_safety_fp32  
    
    libtidl_onnxrt_EP loaded 0x40baed20 
    artifacts_folder                                = ../../../model-artifacts//fnc_safety_fp32/ 
    debug_level                                     = 2 
    target_priority                                 = 0 
    max_pre_empt_delay                              = 340282346638528859811704183484516925440.000000 
    Final number of subgraphs created are : 1, - Offloaded Nodes - 128, Total Nodes - 128 
    In TIDL_createStateInfer 
    Compute on node : TIDLExecutionProvider_TIDL_0_0
    ************ in TIDL_subgraphRtCreate ************ 
     APP: Init ... !!!
    MEM: Init ... !!!
    MEM: Initialized DMA HEAP (fd=5) !!!
    MEM: Init ... Done !!!
    IPC: Init ... !!!
    IPC: Init ... Done !!!
    REMOTE_SERVICE: Init ... !!!
    REMOTE_SERVICE: Init ... Done !!!
       553.354313 s: GTC Frequency = 200 MHz
    APP: Init ... Done !!!
       553.354395 s:  VX_ZONE_INIT:Enabled
       553.354402 s:  VX_ZONE_ERROR:Enabled
       553.354408 s:  VX_ZONE_WARNING:Enabled
       553.354952 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:116] Added target MPU-0 
       553.355065 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:116] Added target MPU-1 
       553.355172 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:116] Added target MPU-2 
       553.355246 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:116] Added target MPU-3 
       553.355255 s:  VX_ZONE_INIT:[tivxInitLocal:136] Initialization Done !!!
       553.355725 s:  VX_ZONE_INIT:[tivxHostInitLocal:101] Initialization Done for HOST !!!
    [C7x_1 ]    553.418064 s: debug_TIDL_alloc: inside TIDL_alloc
    [C7x_1 ]    553.427843 s: debug_TIDL_alloc0: status-0, ok-0 fail--1
    [C7x_1 ]    553.427903 s: debug_TIDL_alloc0: lIdx-9 mem-0 11008 0 lT-29
    [C7x_1 ]    553.427948 s: debug_TIDL_alloc0: lIdx-10 mem-0 17280 0 lT-1
    [C7x_1 ]    553.427983 s: debug_TIDL_alloc0: lIdx-11 mem-0 14848 0 lT-2
    [C7x_1 ]    553.428020 s: debug_TIDL_alloc0: lIdx-12 mem-0 16384 0 lT-1
    [C7x_1 ]    553.428057 s: debug_TIDL_alloc0: lIdx-13 mem-0 16384 0 lT-1
    [C7x_1 ]    553.428091 s: debug_TIDL_alloc0: lIdx-14 mem-0 6528 0 lT-5
    [C7x_1 ]    553.428127 s: debug_TIDL_alloc0: lIdx-15 mem-0 16384 0 lT-1
    [C7x_1 ]    553.428164 s: debug_TIDL_alloc0: lIdx-16 mem-0 16384 0 lT-1
    [C7x_1 ]    553.428196 s: debug_TIDL_alloc0: lIdx-17 mem-0 6528 0 lT-5
    [C7x_1 ]    553.428233 s: debug_TIDL_alloc0: lIdx-18 mem-0 17024 0 lT-1
    [C7x_1 ]    553.428268 s: debug_TIDL_alloc0: lIdx-19 mem-0 17024 0 lT-1
    [C7x_1 ]    553.428304 s: debug_TIDL_alloc0: lIdx-20 mem-0 17152 0 lT-1
    [C7x_1 ]    553.428337 s: debug_TIDL_alloc0: lIdx-21 mem-0 6528 0 lT-5
    [C7x_1 ]    553.428377 s: debug_TIDL_alloc0: lIdx-22 mem-0 17152 0 lT-1
    [C7x_1 ]    553.428415 s: debug_TIDL_alloc0: lIdx-23 mem-0 17152 0 lT-1
    [C7x_1 ]    553.428448 s: debug_TIDL_alloc0: lIdx-24 mem-0 6528 0 lT-5
    [C7x_1 ]    553.428485 s: debug_TIDL_alloc0: lIdx-25 mem-0 18560 0 lT-1
    [C7x_1 ]    553.428524 s: debug_TIDL_alloc0: lIdx-26 mem-0 18688 0 lT-1
    [C7x_1 ]    553.428564 s: debug_TIDL_alloc0: lIdx-27 mem-0 19712 0 lT-1
    [C7x_1 ]    553.428598 s: debug_TIDL_alloc0: lIdx-28 mem-0 6528 0 lT-5
    [C7x_1 ]    553.428641 s: debug_TIDL_alloc0: lIdx-29 mem-0 19712 0 lT-1
    [C7x_1 ]    553.428687 s: debug_TIDL_alloc0: lIdx-30 mem-0 19712 0 lT-1
    [C7x_1 ]    553.428724 s: debug_TIDL_alloc0: lIdx-31 mem-0 6528 0 lT-5
    [C7x_1 ]    553.428768 s: debug_TIDL_alloc0: lIdx-32 mem-0 16256 0 lT-1
    [C7x_1 ]    553.428808 s: debug_TIDL_alloc0: lIdx-33 mem-0 21632 0 lT-1
    [C7x_1 ]    553.428851 s: debug_TIDL_alloc0: lIdx-34 mem-0 22656 0 lT-1
    [C7x_1 ]    553.428894 s: debug_TIDL_alloc0: lIdx-35 mem-0 22784 0 lT-1
    [C7x_1 ]    553.428930 s: debug_TIDL_alloc0: lIdx-36 mem-0 6528 0 lT-5
    [C7x_1 ]    553.428971 s: debug_TIDL_alloc0: lIdx-37 mem-0 22784 0 lT-1
    [C7x_1 ]    553.429015 s: debug_TIDL_alloc0: lIdx-38 mem-0 22784 0 lT-1
    [C7x_1 ]    553.429052 s: debug_TIDL_alloc0: lIdx-39 mem-0 6528 0 lT-5
    [C7x_1 ]    553.429097 s: debug_TIDL_alloc0: lIdx-40 mem-0 17408 0 lT-1
    [C7x_1 ]    553.429124 s: debug_TIDL_alloc0: lIdx-1 mem-0 0 0 lT-39
    [C7x_1 ]    553.429161 s: debug_TIDL_alloc0: lIdx-42 mem-0 6528 0 lT-5
    [C7x_1 ]    553.429206 s: debug_TIDL_alloc0: lIdx-43 mem-0 16256 0 lT-1
    [C7x_1 ]    553.429244 s: debug_TIDL_alloc0: lIdx-46 mem-0 10880 0 lT-29
    [C7x_1 ]    553.429277 s: debug_TIDL_alloc0: lIdx-49 mem-0 0 0 lT-38
    [C7x_1 ]    553.429320 s: debug_TIDL_alloc0: lIdx-44 mem-0 15680 0 lT-1
    [C7x_1 ]    553.429357 s: debug_TIDL_alloc0: lIdx-47 mem-0 10880 0 lT-29
    [C7x_1 ]    553.429390 s: debug_TIDL_alloc0: lIdx-50 mem-0 0 0 lT-38
    [C7x_1 ]    553.429432 s: debug_TIDL_alloc0: lIdx-45 mem-0 15680 0 lT-1
    [C7x_1 ]    553.429469 s: debug_TIDL_alloc0: lIdx-48 mem-0 10880 0 lT-29
    [C7x_1 ]    553.429502 s: debug_TIDL_alloc0: lIdx-51 mem-0 0 0 lT-38
    [C7x_1 ]    553.429535 s: debug_TIDL_alloc0: lIdx-52 mem-0 0 0 lT-38
    [C7x_1 ]    553.429572 s: debug_TIDL_alloc0: lIdx-53 mem-0 10880 0 lT-29
    [C7x_1 ]    553.429606 s: debug_TIDL_alloc0: lIdx-54 mem-0 0 0 lT-38
    [C7x_1 ]    553.429656 s: debug_TIDL_alloc0: lIdx-55 mem-0 5760 0 lT-6
    [C7x_1 ]    553.429697 s: debug_TIDL_alloc0: lIdx-56 mem-0 0 0 lT-38
    [C7x_1 ]    553.429737 s: debug_TIDL_alloc0: lIdx-57 mem-0 10880 0 lT-29
    [C7x_1 ]    553.429772 s: debug_TIDL_alloc0: lIdx-58 mem-0 0 0 lT-38
    [C7x_1 ]    553.429818 s: debug_TIDL_alloc0: lIdx-59 mem-0 5504 0 lT-7
    [C7x_1 ]    553.429860 s: debug_TIDL_alloc0: lIdx-60 mem-0 5760 0 lT-6
    [C7x_1 ]    553.429897 s: debug_TIDL_alloc0: lIdx-61 mem-0 0 0 lT-38
    [C7x_1 ]    553.429935 s: debug_TIDL_alloc0: lIdx-62 mem-0 10880 0 lT-29
    [C7x_1 ]    553.429988 s: debug_TIDL_alloc0: lIdx-63 mem-0 6400 0 lT-8
    [C7x_1 ]    553.430029 s: debug_TIDL_alloc0: lIdx-64 mem-0 6528 0 lT-5
       553.485062 s:  VX_ZONE_ERROR:[ownContextSendCmd:875] Command ack message returned failure cmd_status: -1
    [C7x_1 ]    553.430083 s: debug_TIDL_alloc0: lIdx-65 mem-0 16256 0 lT-1
       553.764017 s:  VX_ZONE_ERROR:[ownNodeKernelInit:590] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
       553.764028 s:  VX_ZONE_ERROR:[ownNodeKernelInit:591] Please be sure the target callbacks have been registered for this core
    [C7x_1 ]    553.430138 s: debug_TIDL_alloc0: lIdx-66 mem-0 16256 0 lT-1
       553.764035 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this
     kernel
       553.764044 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:608] kernel init for node 0, kernel com.ti.tidl:1:3 ... failed !!!
    [C7x_1 ]    553.430166 s: debug_TIDL_alloc0: lIdx-2 mem-0 0 0 lT-39
       553.764059 s:  VX_ZONE_ERROR:[vxVerifyGraph:2159] Node kernel init failed
    [C7x_1 ]    553.430209 s: debug_TIDL_alloc0: lIdx-67 mem-0 6528 0 lT-5
       553.764065 s:  VX_ZONE_ERROR:[vxVerifyGraph:2213] Graph verify failed
    [C7x_1 ]    553.430260 s: debug_TIDL_alloc0: lIdx-68 mem-0 16256 0 lT-1
    [C7x_1 ]    553.430301 s: debug_TIDL_alloc0: lIdx-71 mem-0 10880 0 lT-29
    [C7x_1 ]    553.430338 s: debug_TIDL_alloc0: lIdx-74 mem-0 0 0 lT-38
    TIDL_RT_OVX: ERROR: Verifying TIDL graph ... Failed !!!
    [C7x_1 ]    553.430387 s: debug_TIDL_alloc0: lIdx-69 mem-0 15680 0 lT-1
    TIDL_RT_OVX: ERROR: Verify OpenVX graph failed
    [C7x_1 ]    553.430429 s: debug_TIDL_alloc0: lIdx-72 mem-0 10880 0 lT-29
    [C7x_1 ]    553.430466 s: debug_TIDL_alloc0: lIdx-75 mem-0 0 0 lT-38
    [C7x_1 ]    553.430517 s: debug_TIDL_alloc0: lIdx-70 mem-0 14656 0 lT-1
    [C7x_1 ]    553.430557 s: debug_TIDL_alloc0: lIdx-73 mem-0 10880 0 lT-29
    [C7x_1 ]    553.430594 s: debug_TIDL_alloc0: lIdx-76 mem-0 0 0 lT-38
    [C7x_1 ]    553.430629 s: debug_TIDL_alloc0: lIdx-77 mem-0 0 0 lT-38
    [C7x_1 ]    553.430678 s: debug_TIDL_alloc0: lIdx-78 mem-0 10880 0 lT-29
    [C7x_1 ]    553.430719 s: debug_TIDL_alloc0: lIdx-79 mem-0 0 0 lT-38
    [C7x_1 ]    553.430768 s: debug_TIDL_alloc0: lIdx-80 mem-0 5760 0 lT-6
    [C7x_1 ]    553.430811 s: debug_TIDL_alloc0: lIdx-81 mem-0 0 0 lT-38
    [C7x_1 ]    553.430856 s: debug_TIDL_alloc0: lIdx-82 mem-0 10880 0 lT-29
    [C7x_1 ]    553.430896 s: debug_TIDL_alloc0: lIdx-83 mem-0 0 0 lT-38
    [C7x_1 ]    553.430948 s: debug_TIDL_alloc0: lIdx-84 mem-0 5504 0 lT-7
    [C7x_1 ]    553.430995 s: debug_TIDL_alloc0: lIdx-85 mem-0 5760 0 lT-6
    [C7x_1 ]    553.431037 s: debug_TIDL_alloc0: lIdx-86 mem-0 0 0 lT-38
    [C7x_1 ]    553.431080 s: debug_TIDL_alloc0: lIdx-87 mem-0 10880 0 lT-29
    [C7x_1 ]    553.431141 s: debug_TIDL_alloc0: lIdx-88 mem-0 6400 0 lT-8
    [C7x_1 ]    553.431183 s: debug_TIDL_alloc0: lIdx-89 mem-0 6528 0 lT-5
    [C7x_1 ]    553.431246 s: debug_TIDL_alloc0: lIdx-90 mem-0 16256 0 lT-1
    [C7x_1 ]    553.431310 s: debug_TIDL_alloc0: lIdx-91 mem-0 16256 0 lT-1
    [C7x_1 ]    553.431370 s: debug_TIDL_alloc0: lIdx-92 mem-0 5120 0 lT-21
    [C7x_1 ]    553.431407 s: debug_TIDL_alloc0: lIdx-93 mem-0 6528 0 lT-5
    [C7x_1 ]    553.431470 s: debug_TIDL_alloc0: lIdx-94 mem-0 16256 0 lT-1
    [C7x_1 ]    553.431531 s: debug_TIDL_alloc0: lIdx-95 mem-0 16256 0 lT-1
    [C7x_1 ]    553.431590 s: debug_TIDL_alloc0: lIdx-96 mem-0 17096 0 lT-1
    [C7x_1 ]    553.431636 s: debug_TIDL_alloc0: lIdx-122 mem-0 10880 0 lT-29
    [C7x_1 ]    553.431696 s: debug_TIDL_alloc0: lIdx-123 mem-0 0 0 lT-41
    [C7x_1 ]    553.431752 s: debug_TIDL_alloc0: lIdx-125 mem-0 11904 0 lT-29
    [C7x_1 ]    553.431816 s: debug_TIDL_alloc0: lIdx-103 mem-0 16256 0 lT-1
    [C7x_1 ]    553.431882 s: debug_TIDL_alloc0: lIdx-104 mem-0 15500 0 lT-1
    [C7x_1 ]    553.431952 s: debug_TIDL_alloc0: lIdx-105 mem-0 5642 0 lT-8
    [C7x_1 ]    553.431981 s: debug_TIDL_alloc0: lIdx-3 mem-0 0 0 lT-39
    ************ TIDL_subgraphRtCreate done ************ 
    [C7x_1 ]    553.432027 s: debug_TIDL_alloc0: lIdx-106 mem-0 6528 0 lT-5
    [C7x_1 ]    553.432055 s: debug_TIDL_alloc0: lIdx-4 mem-0 0 0 lT-39
    [C7x_1 ]    553.432104 s: debug_TIDL_alloc0: lIdx-107 mem-0 6528 0 lT-5
    [C7x_1 ]    553.432131 s: debug_TIDL_alloc0: lIdx-5 mem-0 0 0 lT-39
    [C7x_1 ]    553.432162 s: debug_TIDL_alloc0: lIdx-108 mem-0 6528 0 lT-5
    [C7x_1 ]    553.432188 s: debug_TIDL_alloc0: lIdx-6 mem-0 0 0 lT-39
    [C7x_1 ]    553.432218 s: debug_TIDL_alloc0: lIdx-109 mem-0 6528 0 lT-5
    [C7x_1 ]    553.432244 s: debug_TIDL_alloc0: lIdx-7 mem-0 0 0 lT-39
    [C7x_1 ]    553.432275 s: debug_TIDL_alloc0: lIdx-110 mem-0 6528 0 lT-5
    [C7x_1 ]    553.432301 s: debug_TIDL_alloc0: lIdx-8 mem-0 0 0 lT-39
    [C7x_1 ]    553.432331 s: debug_TIDL_alloc0: lIdx-111 mem-0 6528 0 lT-5
    [C7x_1 ]    553.432397 s: debug_TIDL_alloc0: lIdx-112 mem-0 14848 0 lT-2
    [C7x_1 ]    553.432471 s: debug_TIDL_alloc0: lIdx-113 mem-0 5642 0 lT-8
    [C7x_1 ]    553.432520 s: debug_TIDL_alloc0: lIdx-114 mem-0 6528 0 lT-5
    [C7x_1 ]    553.432589 s: debug_TIDL_alloc0: lIdx-115 mem-0 5642 0 lT-8
    [C7x_1 ]    553.432666 s: debug_TIDL_alloc0: lIdx-116 mem-0 5642 0 lT-8
    [C7x_1 ]    553.432723 s: debug_TIDL_alloc0: lIdx-117 mem-0 7424 0 lT-5
    [C7x_1 ]    553.432776 s: debug_TIDL_alloc0: lIdx-119 mem-0 11904 0 lT-29
    [C7x_1 ]    553.432836 s: debug_TIDL_alloc0: lIdx-97 mem-0 5248 0 lT-21
    [C7x_1 ]    553.432880 s: debug_TIDL_alloc0: lIdx-41 mem-0 16256 0 lT-1
    [C7x_1 ]    553.432918 s: debug_TIDL_alloc0: lIdx-98 mem-0 6528 0 lT-5
    [C7x_1 ]    553.432984 s: debug_TIDL_alloc0: lIdx-99 mem-0 16384 0 lT-1
    [C7x_1 ]    553.433049 s: debug_TIDL_alloc0: lIdx-100 mem-0 16384 0 lT-1
    [C7x_1 ]    553.433110 s: debug_TIDL_alloc0: lIdx-101 mem-0 16384 0 lT-1
    [C7x_1 ]    553.433168 s: debug_TIDL_alloc0: lIdx-102 mem-0 16384 0 lT-1
    [C7x_1 ]    553.433216 s: debug_TIDL_alloc0: lIdx-120 mem-0 11904 0 lT-29
    [C7x_1 ]    553.433658 s: PREEMPTION: Requesting memory of size 8159232 for targetPriority = 512
    [C7x_1 ]    553.433678 s: 
    [C7x_1 ]    553.433696 s: --------------------------------------------
    [C7x_1 ]    553.433721 s: TIDL Memory size requiement (record wise):
    [C7x_1 ]    553.433761 s: MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
    [C7x_1 ]    553.433805 s: 0           , DDR Cacheable       , Persistent  ,  128, 19.25   , 0x00000000
    [C7x_1 ]    553.433847 s: 1           , DDR Cacheable       , Persistent  ,  128, 0.64    , 0x00000000
    [C7x_1 ]    553.433886 s: 2           , L1D                 , Scratch     ,  128, 16.00   , 0x00000000
    [C7x_1 ]    553.433926 s: 3           , L2                  , Scratch     ,  128, 448.00  , 0x00000000
    [C7x_1 ]    553.433965 s: 4           , L3/MSMC             , Scratch     ,  128, 7968.00 , 0x00000000
    [C7x_1 ]    553.434004 s: 5           , DDR Cacheable       , Persistent  ,  128, 24726.75, 0x00000000
    [C7x_1 ]    553.434043 s: 6           , DDR Cacheable       , Scratch     ,  128, 15.50   , 0x00000000
    [C7x_1 ]    553.434082 s: 7           , DDR Cacheable       , Persistent  ,  128, 9461.25 , 0x00000000
    [C7x_1 ]    553.434121 s: 8           , DDR Cacheable       , Scratch     ,  128, 0.13    , 0x00000000
    [C7x_1 ]    553.434160 s: 9           , DDR Cacheable       , Scratch     ,  128, 3.13    , 0x00000000
    [C7x_1 ]    553.434199 s: 10          , DDR Cacheable       , Persistent  ,  128, 1400.36 , 0x00000000
    [C7x_1 ]    553.434238 s: 11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0x00000000
    [C7x_1 ]    553.434277 s: 12          , DDR Cacheable       , Persistent  ,  128, 7968.00 , 0x00000000
    [C7x_1 ]    553.434316 s: 13          , DDR Cacheable       , Persistent  ,  128, 24921.25, 0x00000000
    
    ***************Running_Inference Section **********
    [C7x_1 ]    553.434355 s: 14          , DDR Cacheable       , Persistent  ,  128, 0.00    , 0x00000000
    [C7x_1 ]    553.434382 s: --------------------------------------------
    
    [C7x_1 ]    553.434406 s: Total memory size requirement (space wise):
    [C7x_1 ]    553.434424 s: Mem Space , Size(KBytes)
    [C7x_1 ]    553.434440 s: L1D       , 16.00   
    [C7x_1 ]    553.434455 s: L2        , 448.00  
    [C7x_1 ]    553.434471 s: L3/MSMC   , 7968.00 
    [C7x_1 ]    553.434488 s: DDR Cacheable, 69028.50
    [C7x_1 ]    553.434509 s: --------------------------------------------
    [C7x_1 ]    553.434543 s: NOTE: Memory requirement in host emulation can be different from the same on EVM
    [C7x_1 ]    553.434581 s:       To get the actual TIDL memory requirement make sure to run on EVM with 
    [C7x_1 ]    553.434603 s:       debugTraceLevel = 2
    [C7x_1 ]    553.434611 s: 
    [C7x_1 ]    553.434630 s: --------------------------------------------
    [C7x_1 ]    553.435352 s: TIDL init call from ivision API 
    [C7x_1 ]    553.435366 s: 
    [C7x_1 ]    553.435383 s: --------------------------------------------
    [C7x_1 ]    553.435406 s: TIDL Memory size requiement (record wise):
    [C7x_1 ]    553.435445 s: MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
    [C7x_1 ]    553.435486 s: 0           , DDR Cacheable       , Persistent  ,  128, 19.25   , 0x1b30bd00
    [C7x_1 ]    553.435526 s: 1           , DDR Cacheable       , Persistent  ,  128, 0.64    , 0x1b310b00
    [C7x_1 ]    553.435565 s: 2           , L1D                 , Scratch     ,  128, 16.00   , 0x64e00000
    [C7x_1 ]    553.435605 s: 3           , L2                  , Scratch     ,  128, 448.00  , 0x64800000
    [C7x_1 ]    553.435646 s: 4           , L3/MSMC             , Scratch     ,  128, 7968.00 , 0x70020000
    [C7x_1 ]    553.435689 s: 5           , DDR Cacheable       , Persistent  ,  128, 24726.75, 0x1b310f00
    [C7x_1 ]    553.435728 s: 6           , DDR Cacheable       , Scratch     ,  128, 15.50   , 0x00000000
    [C7x_1 ]    553.435768 s: 7           , DDR Cacheable       , Persistent  ,  128, 9461.25 , 0x1cb36b00
    [C7x_1 ]    553.435808 s: 8           , DDR Cacheable       , Scratch     ,  128, 0.13    , 0x00004000
    [C7x_1 ]    553.435847 s: 9           , DDR Cacheable       , Scratch     ,  128, 3.13    , 0x00004400
    [C7x_1 ]    553.435886 s: 10          , DDR Cacheable       , Persistent  ,  128, 1400.36 , 0x1d474100
    [C7x_1 ]    553.435926 s: 11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0x00005400
    [C7x_1 ]    553.435965 s: 12          , DDR Cacheable       , Persistent  ,  128, 7968.00 , 0x1d5d2400
    This is Lucid Model for image ../../../lucid/data_onnx/test_images/img0001.png
    [C7x_1 ]    553.436004 s: 13          , DDR Cacheable       , Persistent  ,  128, 24921.25, 0x1dd9a500
    [C7x_1 ]    553.436043 s: 14          , DDR Cacheable       , Persistent  ,  128, 0.00    , 0x1f5f0b00
    [C7x_1 ]    553.436071 s: --------------------------------------------
    [C7x_1 ]    553.436094 s: Total memory size requirement (space wise):
    [C7x_1 ]    553.436112 s: Mem Space , Size(KBytes)
    [C7x_1 ]    553.436128 s: L1D       , 16.00   
    [C7x_1 ]    553.436143 s: L2        , 448.00  
    [C7x_1 ]    553.436159 s: L3/MSMC   , 7968.00 
    [C7x_1 ]    553.436175 s: DDR Cacheable, 69028.50
    [C7x_1 ]    553.436197 s: --------------------------------------------
    [C7x_1 ]    553.436231 s: NOTE: Memory requirement in host emulation can be different from the same on EVM
    [C7x_1 ]    553.436268 s:       To get the actual TIDL memory requirement make sure to run on EVM with 
    [C7x_1 ]    553.436290 s:       debugTraceLevel = 2
    [C7x_1 ]    553.436298 s: 
    [C7x_1 ]    553.436317 s: --------------------------------------------
     *******   In TIDL_subgraphRtInvoke  ******** 
    [C7x_1 ]    553.438618 s: Alg Init for Layer # -    9
    [C7x_1 ]    553.438776 s: debug_TIDL_init0: lIdx-9 0 11008 0
    [C7x_1 ]    553.438801 s: Alg Init for Layer # -   10
    [C7x_1 ]    553.439031 s: debug_TIDL_init0: lIdx-10 0 17280 0
    [C7x_1 ]    553.439057 s: Alg Init for Layer # -   11
    [C7x_1 ]    553.439215 s: debug_TIDL_init0: lIdx-11 0 14848 0
    [C7x_1 ]    553.439239 s: Alg Init for Layer # -   12
    [C7x_1 ]    553.439626 s: debug_TIDL_init0: lIdx-12 0 16384 0
    [C7x_1 ]    553.439660 s: Alg Init for Layer # -   13
    [C7x_1 ]    553.440031 s: debug_TIDL_init0: lIdx-13 0 16384 0
    [C7x_1 ]    553.440058 s: Alg Init for Layer # -   14
    [C7x_1 ]    553.440266 s: debug_TIDL_init0: lIdx-14 0 6528 0
    [C7x_1 ]    553.440291 s: Alg Init for Layer # -   15
    [C7x_1 ]    553.440660 s: debug_TIDL_init0: lIdx-15 0 16384 0
    [C7x_1 ]    553.440688 s: Alg Init for Layer # -   16
    [C7x_1 ]    553.441063 s: debug_TIDL_init0: lIdx-16 0 16384 0
    [C7x_1 ]    553.441089 s: Alg Init for Layer # -   17
    [C7x_1 ]    553.441292 s: debug_TIDL_init0: lIdx-17 0 6528 0
    [C7x_1 ]    553.441317 s: Alg Init for Layer # -   18
    [C7x_1 ]    553.441523 s: debug_TIDL_init0: lIdx-18 0 17024 0
    [C7x_1 ]    553.441549 s: Alg Init for Layer # -   19
    [C7x_1 ]    553.441975 s: debug_TIDL_init0: lIdx-19 0 17024 0
    [C7x_1 ]    553.442002 s: Alg Init for Layer # -   20
    [C7x_1 ]    553.442704 s: debug_TIDL_init0: lIdx-20 0 17152 0
    [C7x_1 ]    553.442730 s: Alg Init for Layer # -   21
    [C7x_1 ]    553.442934 s: debug_TIDL_init0: lIdx-21 0 6528 0
    [C7x_1 ]    553.442958 s: Alg Init for Layer # -   22
    [C7x_1 ]    553.443653 s: debug_TIDL_init0: lIdx-22 0 17152 0
    [C7x_1 ]    553.443680 s: Alg Init for Layer # -   23
    [C7x_1 ]    553.444392 s: debug_TIDL_init0: lIdx-23 0 17152 0
    [C7x_1 ]    553.444419 s: Alg Init for Layer # -   24
    [C7x_1 ]    553.444624 s: debug_TIDL_init0: lIdx-24 0 6528 0
    [C7x_1 ]    553.444655 s: Alg Init for Layer # -   25
    [C7x_1 ]    553.444957 s: debug_TIDL_init0: lIdx-25 0 18560 0
    [C7x_1 ]    553.444984 s: Alg Init for Layer # -   26
    [C7x_1 ]    553.446095 s: debug_TIDL_init0: lIdx-26 0 18688 0
    [C7x_1 ]    553.446122 s: Alg Init for Layer # -   27
    [C7x_1 ]    553.448168 s: debug_TIDL_init0: lIdx-27 0 19712 0
    [C7x_1 ]    553.448196 s: Alg Init for Layer # -   28
    [C7x_1 ]    553.448408 s: debug_TIDL_init0: lIdx-28 0 6528 0
    [C7x_1 ]    553.448432 s: Alg Init for Layer # -   29
    [C7x_1 ]    553.450459 s: debug_TIDL_init0: lIdx-29 0 19712 0
    [C7x_1 ]    553.450488 s: Alg Init for Layer # -   30
    [C7x_1 ]    553.452517 s: debug_TIDL_init0: lIdx-30 0 19712 0
    [C7x_1 ]    553.452544 s: Alg Init for Layer # -   31
    [C7x_1 ]    553.452769 s: debug_TIDL_init0: lIdx-31 0 6528 0
    [C7x_1 ]    553.452792 s: Alg Init for Layer # -   32
    [C7x_1 ]    553.453063 s: debug_TIDL_init0: lIdx-32 0 16256 0
    [C7x_1 ]    553.453090 s: Alg Init for Layer # -   33
    [C7x_1 ]    553.453712 s: debug_TIDL_init0: lIdx-33 0 21632 0
    [C7x_1 ]    553.453739 s: Alg Init for Layer # -   34
    [C7x_1 ]    553.457535 s: debug_TIDL_init0: lIdx-34 0 22656 0
    [C7x_1 ]    553.457563 s: Alg Init for Layer # -   35
    [C7x_1 ]    553.464956 s: debug_TIDL_init0: lIdx-35 0 22784 0
    [C7x_1 ]    553.464985 s: Alg Init for Layer # -   36
    [C7x_1 ]    553.465206 s: debug_TIDL_init0: lIdx-36 0 6528 0
    [C7x_1 ]    553.465230 s: Alg Init for Layer # -   37
    [C7x_1 ]    553.472579 s: debug_TIDL_init0: lIdx-37 0 22784 0
    [C7x_1 ]    553.472607 s: Alg Init for Layer # -   38
    [C7x_1 ]    553.479976 s: debug_TIDL_init0: lIdx-38 0 22784 0
    [C7x_1 ]    553.480004 s: Alg Init for Layer # -   39
    [C7x_1 ]    553.480226 s: debug_TIDL_init0: lIdx-39 0 6528 0
    [C7x_1 ]    553.480250 s: Alg Init for Layer # -   40
       554.784391 s:  VX_ZONE_ERROR:[ownContextSendCmd:875] Command ack message returned failure cmd_status: -1
    [C7x_1 ]    553.481369 s: debug_TIDL_init0: lIdx-40 0 17408 0
       555.096510 s:  VX_ZONE_ERROR:[ownNodeKernelInit:590] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
       555.096520 s:  VX_ZONE_ERROR:[ownNodeKernelInit:591] Please be sure the target callbacks have been registered for this core
    [C7x_1 ]    553.481396 s: Alg Init for Layer # -    1
       555.096527 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this
     kernel
       555.096534 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:608] kernel init for node 0, kernel com.ti.tidl:1:3 ... failed !!!
    [C7x_1 ]    553.481549 s: debug_TIDL_init0: lIdx-1 0 0 0
       555.096547 s:  VX_ZONE_ERROR:[vxVerifyGraph:2159] Node kernel init failed
    [C7x_1 ]    553.481576 s: Alg Init for Layer # -   42
       555.096553 s:  VX_ZONE_ERROR:[vxVerifyGraph:2213] Graph verify failed
    [C7x_1 ]    553.481802 s: debug_TIDL_init0: lIdx-42 0 6528 0
    [C7x_1 ]    553.481828 s: Alg Init for Layer # -   43
    [C7x_1 ]    553.482060 s: debug_TIDL_init0: lIdx-43 0 16256 0
    [C7x_1 ]    553.482085 s: Alg Init for Layer # -   46
       555.096604 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:885] graph is not in a state required to be scheduled
    [C7x_1 ]    553.482231 s: debug_TIDL_init0: lIdx-46 0 10880 0
       555.096612 s:  VX_ZONE_ERROR:[vxProcessGraph:813] schedule graph failed
       555.096618 s:  VX_ZONE_ERROR:[vxProcessGraph:818] wait graph failed
    [C7x_1 ]    553.482254 s: Alg Init for Layer # -   49
    ERROR: Running TIDL graph ... Failed !!!
    [C7x_1 ]    553.482367 s: debug_TIDL_init0: lIdx-49 0 0 0
    Sub Graph Stats 1184.000000 332035.000000 14740169020138048.000000 
    [C7x_1 ]    553.482389 s: Alg Init for Layer # -   44
    *******  TIDL_subgraphRtInvoke done  ******** 
    [C7x_1 ]    553.482591 s: debug_TIDL_init0: lIdx-44 0 15680 0
    [C7x_1 ]    553.482616 s: Alg Init for Layer # -   47
    [C7x_1 ]    553.482766 s: debug_TIDL_init0: lIdx-47 0 10880 0
    [C7x_1 ]    553.482790 s: Alg Init for Layer # -   50
    [C7x_1 ]    553.482904 s: debug_TIDL_init0: lIdx-50 0 0 0
    [C7x_1 ]    553.482926 s: Alg Init for Layer # -   45
    [C7x_1 ]    553.483137 s: debug_TIDL_init0: lIdx-45 0 15680 0
    [C7x_1 ]    553.483162 s: Alg Init for Layer # -   48
    [C7x_1 ]    553.483306 s: debug_TIDL_init0: lIdx-48 0 10880 0
    [C7x_1 ]    553.483330 s: Alg Init for Layer # -   51
    [C7x_1 ]    553.483444 s: debug_TIDL_init0: lIdx-51 0 0 0
    [C7x_1 ]    553.483467 s: Alg Init for Layer # -   52
    [C7x_1 ]    553.483564 s: debug_TIDL_init0: lIdx-52 0 0 0
    [C7x_1 ]    553.483586 s: Alg Init for Layer # -   53
    [C7x_1 ]    553.483724 s: debug_TIDL_init0: lIdx-53 0 10880 0
    [C7x_1 ]    553.483748 s: Alg Init for Layer # -   54
    [C7x_1 ]    553.483860 s: debug_TIDL_init0: lIdx-54 0 0 0
    [C7x_1 ]    553.483884 s: Alg Init for Layer # -   55
    [C7x_1 ]    553.484076 s: debug_TIDL_init0: lIdx-55 0 5504 0
    [C7x_1 ]    553.484099 s: Alg Init for Layer # -   56
    [C7x_1 ]    553.484212 s: debug_TIDL_init0: lIdx-56 0 0 0
    [C7x_1 ]    553.484235 s: Alg Init for Layer # -   57
    [C7x_1 ]    553.484364 s: debug_TIDL_init0: lIdx-57 0 10880 0
    [C7x_1 ]    553.484389 s: Alg Init for Layer # -   58
    [C7x_1 ]    553.484500 s: debug_TIDL_init0: lIdx-58 0 0 0
    [C7x_1 ]    553.484522 s: Alg Init for Layer # -   59
    [C7x_1 ]    553.484696 s: Output Transpose is not supported on this device.. 
    [C7x_1 ]    553.484746 s: WorkloadUnitExec_Init: initParams->linkInitParams[linkIdx].initFuncPtr Failed, Link Id 31272731568 
    [C7x_1 ]    553.484776 s: debug_TIDL_init0: lIdx-59 0 5504 0
    [C7x_1 ]    553.484798 s:  VX_ZONE_ERROR:[tivxAlgiVisionCreate:335] Calling ialg.algInit failed with status = 1
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    [C7x_1 ]    553.484874 s:  VX_ZONE_ERROR:[tivxKernelTIDLCreate:926] tivxAlgiVisionCreate returned NULL
    [C7x_1 ]    554.784177 s:  VX_ZONE_ERROR:[tivxKernelTIDLCreate:910] Network version - 0x00000000, Expected version - 0x20240401
    
    
    ***************Running_Benchmark_Section **********
    
    
    ***************Running_Inference Section **********
    
    This is Lucid Model for image ../../../lucid/data_onnx/test_images/img0222.png
    *******   In TIDL_subgraphRtInvoke  ******** 
       556.242498 s:  VX_ZONE_ERROR:[ownContextSendCmd:875] Command ack message returned failure cmd_status: -1
       556.242518 s:  VX_ZONE_ERROR:[ownNodeKernelInit:590] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
       556.242525 s:  VX_ZONE_ERROR:[ownNodeKernelInit:591] Please be sure the target callbacks have been registered for this core
       556.242531 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this
     kernel
       556.242538 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:608] kernel init for node 0, kernel com.ti.tidl:1:3 ... failed !!!
       556.242549 s:  VX_ZONE_ERROR:[vxVerifyGraph:2159] Node kernel init failed
       556.242555 s:  VX_ZONE_ERROR:[vxVerifyGraph:2213] Graph verify failed
       556.242600 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:885] graph is not in a state required to be scheduled
       556.242606 s:  VX_ZONE_ERROR:[vxProcessGraph:813] schedule graph failed
       556.242611 s:  VX_ZONE_ERROR:[vxProcessGraph:818] wait graph failed
    ERROR: Running TIDL graph ... Failed !!!
    Sub Graph Stats 1388.000000 1043.000000 14740169020138048.000000 
    *******  TIDL_subgraphRtInvoke done  ******** 
    [C7x_1 ]    556.242333 s:  VX_ZONE_ERROR:[tivxKernelTIDLCreate:910] Network version - 0x00000000, Expected version - 0x20240401
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    ***************Running_Benchmark_Section **********
    
    
    ***************Running_Inference Section **********
    
    This is Lucid Model for image ../../../lucid/data_onnx/test_images/img0278.png
    *******   In TIDL_subgraphRtInvoke  ******** 
       557.086369 s:  VX_ZONE_ERROR:[ownContextSendCmd:875] Command ack message returned failure cmd_status: -1
       557.086391 s:  VX_ZONE_ERROR:[ownNodeKernelInit:590] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
       557.086397 s:  VX_ZONE_ERROR:[ownNodeKernelInit:591] Please be sure the target callbacks have been registered for this core
       557.086403 s:  VX_ZONE_ERROR:[ownNodeKernelInit:592] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this
     kernel
       557.086411 s:  VX_ZONE_ERROR:[ownGraphNodeKernelInit:608] kernel init for node 0, kernel com.ti.tidl:1:3 ... failed !!!
       557.086420 s:  VX_ZONE_ERROR:[vxVerifyGraph:2159] Node kernel init failed
       557.086426 s:  VX_ZONE_ERROR:[vxVerifyGraph:2213] Graph verify failed
       557.086471 s:  VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:885] graph is not in a state required to be scheduled
       557.086477 s:  VX_ZONE_ERROR:[vxProcessGraph:813] schedule graph failed
       557.086483 s:  VX_ZONE_ERROR:[vxProcessGraph:818] wait graph failed
    ERROR: Running TIDL graph ... Failed !!!
    Sub Graph Stats 1411.000000 1037.000000 14740169020138048.000000 
    *******  TIDL_subgraphRtInvoke done  ******** 
    [C7x_1 ]    557.086210 s:  VX_ZONE_ERROR:[tivxKernelTIDLCreate:910] Network version - 0x00000000, Expected version - 0x20240401
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    ***************Running_Benchmark_Section **********
    
     The post proceessing is already done 
    
     
    Completed_Model :     1, Name : fnc_safety_fp32                                   , Total time : 3706575053737.70, Offload Time :     111.37 , DDR RW MBs : 0, Output File : p
    y_out_fnc_safety_fp32_img0278.png 
     
     
    ************ in TIDL_subgraphRtDelete ************ 
        557.819010 s:  VX_ZONE_INIT:[tivxHostDeInitLocal:115] De-Initialization Done for HOST !!!
       557.823434 s:  VX_ZONE_INIT:[tivxDeInitLocal:204] De-Initialization Done !!!
    APP: Deinit ... !!!
    REMOTE_SERVICE: Deinit ... !!!
    REMOTE_SERVICE: Deinit ... Done !!!
    IPC: Deinit ... !!!
    IPC: DeInit ... Done !!!
    MEM: Deinit ... !!!
    DDR_SHARED_MEM: Alloc's: 10 alloc's of 276211276 bytes 
    DDR_SHARED_MEM: Free's : 10 free's  of 276211276 bytes 
    DDR_SHARED_MEM: Open's : 0 allocs  of 0 bytes 
    MEM: Deinit ... Done !!!
    APP: Deinit ... Done !!!