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AM6442: How to configure PLL dividers (HSDIVs) using Linux or U-Boot

Patrick Oppenlander
Prodigy 30 points
Part Number: AM6442

Tool/software:

Hi,

we need to reconfigure the MAIN_PLL1 (PER0 PLL) HSDIV1 output from 160MHz to 128MHz to achieve the UART baud rate required for our project.

I've confirmed this works by direcly writing to the PLL1_HSDIV_CTRL1 register from U-Boot (i.e. hack a "mw.l 0x681084 0x0000800e 1" into the boot script), but this hardly seems like a sensible way to do it.

Is there a recommended/supported way of configuring the PLL dividers in the Linux or U-Boot?

Thanks,

Patrick

  • 0
    TI__Guru**** 167581 points

    Hi Patrick,

    This can be done in the board device tree. The following device tree patch shows how to do it for MAIN UART0 on AM64x GPEVM. If you need this for a different UART port, you would have to modify this in the corresponding UART DT mode, and change the clock ID "146" to the one corresponds to the specific UART.

    index 4f78ca012c8e..15c8944aa184 100644
    --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
    +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
    @@ -444,6 +444,10 @@ &main_uart0 {
            status = "okay";
            pinctrl-names = "default";
            pinctrl-0 = <&main_uart0_pins_default>;
    +       /delete-property/ clock-frequency;
    +       assigned-clocks = <&k3_clks 146 0>;
    +       assigned-clock-parents = <&k3_clks 146 2>;
    +       assigned-clock-rates = <128000000>;
     };
     
     /* main_uart1 is reserved for firmware usage */