We are using an 8-bit micron 4Gb micron flash device, it has internally 5 bit error detection and 4 bit error correction. It allows 1 partial page write per ecc area, so our 2048 sector can be split up into four 512 byte writes and still use the internal ECC correctly.
The OMAPL138 has 4 bit something or other, I don't know much about the emifa, and I'd be reading about it now if i didn't have to go out, so to save some time I'm asking here. Do I need to split up the rights and reads into the 512 byte sections to properly work with the EMIFA ecc registers?
We are trying to adapt our low level code to work with another block driver, which is expecting to turn on the ECC and calculate it out, toss the sector into the nand chip, and then finish any ECC calculations and write the spare page. Ours breaks up the write into four sequences of enabling the ECC and a 512 byte write, before finishing up and writing the spare page.
It would be much easier to massage our code to work with theirs but if i can't it wouldn't be too much more work going the other way.
