TDA4VH-Q1: Power sequence delay between rails

Tony Tang

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Tool/software:

The power sequence foot marked time delay, but it is between ramp up start point, did not mark delay requirement after reaching required stable level. is there such delay requirement?

If the previous rail start ramp up first, but ramp up slowly, reach stable level same as later rail, or <1ms, is it acceptable for TDA4VH?

6 months ago

0 Bill McCracken 5 months ago

TI__Expert 5885 points

The slew rates of both rails should be similar in order to ensure the earlier/1st rail has reached min operational voltage level before the later/2nd rail as shown in the diagram. Any potential variation in slew rates changing over temp & across process should never allow the later/2nd rail to reach min operational voltage before the earlier/1st rail. The recommended power components use controlled slew rates to avoid this condition.

0 Tony Tang 5 months ago in reply to Bill McCracken

TI__Mastermind 27272 points

Hi Bill,

So the time delay(0ms->2ms->3ms->4ms) between rail is not strict required? just need to ensure the later rail power up after previous rail, and not over slew rate.