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DRA821U: QSPI Clock speed

Kaushal C
Intellectual 470 points

Part Number: DRA821U

Tool/software:

Dear team,

We are using OSPI controller and Flash device IS25WP016D-JNLE. Here CPU is the master and datasheet suggest clock speed of 133MHz(Correct me if I'm wrong). 

So when we set it to 133MHz and probe using oscilloscope we observe clock around 76MHz and read/write fails. But when we set to 50MHz clock read/write will pass but oscilloscope reads around 42MHz clock frequency. Why is this deviation and please confirm if max clock frequency is just 50MHz

Regards,
Kaushal

  • 0
    TI__Mastermind 42135 points

    Hi,

    I forward the thread to our experts. Please expect some delay in response.

    Regards,

    Karthik

  • 0 in reply to Parth Nagpal
    TI__Mastermind 22280 points

    Kaushal,

    The OSPI should be capable of 133MHz in some modes; the datasheet clip you have provided looks like it is from the GPMC rather than the OSPI... The datasheet section 7.9.5.18 deals with the OSPI.

    The clock for the OSPI comes from either PLL1 (HSDIV4) or PLL2 (HSDIV4) as shown in Figure 12-1974 in the TRM. Additionally, Figure 12-1976 shows a divider in the path from the RCLK to the pin. What I am trying to say is that there are several places that the clock frequency could have been adjusted and I'm not sure that this is a hardware restriction.

    Kevin

  • 0 in reply to Kevin Lavery
    Intellectual 470 points

    Hi,

    Kevin Lavery said:

    What I am trying to say is that there are several places that the clock frequency could have been adjusted and I'm not sure that this is a hardware restriction.

    Kevin

    So you mean to say when we set it to 50Mhz due to this when probed we are getting around 42Mhz?

    Regards,
    Kaushal

  • 0 in reply to Kaushal C
    TI__Mastermind 22280 points

    Kaushal,

    No, I am not saying that. 

    Determine the input clock frequency to the OSPI

    • read CTRLMMR_MCU_OSPI0_CLKSEL to determine what is driving the OSPI functional clock
    • read the PLL registers for whichever PLL is being used

    Then, can you read the OSPI register -- OSPI_CONFIG_REG which contains the Master Mode Baud Rate divider.

    I would expect the RCLK and OCLK to have an integral relationship (at least in Master mode).

    Kevin