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AM6422: Power up / Down sequencing

Alex Paul
Expert 5685 points

Part Number: AM6422

Tool/software:

Dear Experts,

Currently I am struggeling to understand our requirements for power up and power down sequencing.

Our Power down Sequencing states:  VDD_CORE should be ramped down parallel or later than 

the 0.85 V supply lines.

Considering the power up there it is also allowed for VDD_CORE to ramp up/down before or after VDDS_DDR.

So, why is this not allowed during power down?

I would like to understand the exact requirements here and were they orginate from.

Especially knowing that the PMIC that is intended to use  (TPS6521903) is switching of the 3.3 V load switch at the same time as 0V75 ramps down.

When 3V3 have more capacities on rail this will discharge slower especially when considering that 0.75 is activly discharged.

Regards,

Alex

  • 0
    TI__Guru**** 210210 points

    Hello Alex, 

    Thank you for the query.

    I need to check with the device expert.

    Please expect some delay.

    Regards,

    Sreenivasa

  • +1 in reply to Kallikuppa Sreenivasa
    TI__Guru 63605 points

    Did you read notes 8 and 9 associated with the power-up sequence and notes 3 and 4 associated with the power-down sequence?

    These notes are describing why VDD_CORE is shown in two waveforms and identifies which waveform applies to VDD_CORE based on the operating voltage.

    There is only one firm requirement for AM64x power-down. See note 5 associated with the power-down sequence. 

    The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE + 0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is operating at 0.85V.

    Regards,
    Paul