Tool/software:
Hi Team,
We have to implement the DSS 24 Bit -> GVIF-2 interface connected to HUD as shown in the below block diagram:
We are planning to use the following SOC pins (AMP62P) to implement the above block:
As you can see that we have VOUT0_HSYNC (AC20) and VOUT0_VSYNC (W20) pins dedicated to HSYNC and VSYNC functionality.
Can we control the polarity of the HSYNC and VSYNC to meet the above waveform requirement of the HUD?
The HSYNC and VSYNC polarity of the video fed to the HUD display from SOC is shown in below waveform:
As per the TRM document of AMP62P (AM62P54TM-1400) the following section suggests we can invert the polarity of the HSYNC and VSYNC using the registers.
Please confirm if the above understanding is correct.
