How to share code among cores

It should be as simple as putting the code/text section in shared memory. This is often accomplished in CCS or the SECTIONS part of a linker file, but there are likely other ways. If this memory is cacheable (and there is L1P cache), then the code will be cached in each core as it reads instructions.

I understand that aspect of it. I'm more concerned about the linking process, with partial linking and the creating of a proper set of unique executables for each core, sharing code in either shared SRAM or external DDR memory. How does that work into the XDC build process?

Is there any info out there regarding partial linking and the XDC build process?

for other readers of this thread, the discussion has moved to here:

http://e2e.ti.com/support/embedded/f/355/p/140762/507847.aspx#507847

in fact, this thread is moved to here.

http://e2e.ti.com/support/embedded/f/355/t/140754.aspx