AM6422: linux CPSW eth0 can not ping

Hi,

Please attach the results of the following:

- only connect one ethernet interface with a link partner

- console boot log, looking for driver initialization

- determine if the interfaces are defined - ifconfig -a 

- check if there is an ethernet link - ethtool eth0

- check if the HW mac statics are showing packets flowing - ethtool -S eth0

(please not cut and paste directly into the post).

Best Regards,

Schuyler

Hi,

Thank you for your reply，I did it as you said.The eth0 network port is directly connected to the computer network port, and only this one interface is connected.

The following information appears when uboot starts。Since we made the hardware ourselves, the eeprom address has not changed, but the one used is inconsistent with the evaluation board, and IIC0 is used. Which file should be modified for this error?
EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1
Net: eth0: ethernet@8000000port@1

Regards

Hi，

Follow the instructions and the information is as follows:编辑2.C

Hi,

Thank you for the data you collected. The HW statistics are showing that you are sending TX frames but are not receiving any. If the link partner is a Linux PC you should be able to use the same ethtool -S for the Ethernet interface being used. You are looking to see if the PC is receiving frames from your board without errors. If you are using a Linux pc for the link partner please attach the ethtool -S for the interface. Otherwise you could try using wireshark to see if you are seeing packets from your board.

Could you please attach the boot log from the console?

Best Regards,

Schuyler

Hi，

I will try to do this.And I also have another questions.

1.EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1
Net: eth0: ethernet@8000000port@1

Which file should be modified for this error?

2.Serial port 1 is configured as a backup in the device tree for firmware. Can I use it as a normal serial port? How can I modify the device tree file to use serial port 1 as a normal serial port?

3、Our hardware uses the MII interface Ethernet of ICSSG0. How to configure it in the device tree? Is there any relevant device tree example for reference?

Hi,

Unfortunately I specialize in the CPSW Ethernet interface, these other questions you are asking will have to be asked individually on e2e so they get routed to the correct expert. 

I can provide some answers on the ICSSG but I still recommend submitting another e2e post for this question. I would recommend using the SYSCONFIG tool to get the pin mux portion for the DTS and then look at the AM64 GP EVM DTS file. Referencing the node for PRU and setting the interface mode to MII mode would be a start. But please file another e2e post for this question.

Best Regards,

Schuyler

Hi，

Thank you for your reply! My CPSW eth0 is still in the original state. Can you tell me how to get the boot log? This is my first time to use Linux.

Hi,

The easiest answer I can think is to look for how to log screen output to a file with the console application you are using.  But this may depend on the application you are using to look at the console output.

Best Regards,

Schuyler

Hi，

At present, I have not added any application program. Based on the original evaluation board, the kernel has not been modified, but the device tree has been modified. Only one of the two network ports of the CPSW used can be pinged, but the other one can recognize the connection when the network cable is plugged in and out, but it cannot be pinged. Can you confirm whether there is a problem with the device tree file I sent before? And other suspicious points?

Hello,

I'm a colleague of Schuyler who will be helping out with your inquiry

I have two comments to make regarding this issue:

1. In your DTS I noticed that your cpsw3g_mdio node is configured with "reg=<1>" for "cpsw3g_phy0" and "reg=<0>" for "cpsw3g_phy1". This doesn't seem consistent to me, was there a particular reason for this?

&cpsw3g_mdio {
	cpsw3g_phy0: ethernet-phy@0 {
		reg = <1>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};

	cpsw3g_phy1: ethernet-phy@1 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};
};

2. It seems like you are testing both CPSW ethernet ports. What IP address did you configure both ports? Please note that if both ports are configured on the same subnet then you will see a very similar result to what you reported (one port does ping and the other does not). This is because when on the same subnet, the response from the linked partner to the ping test might get received by the other port rather than getting received by the port under test. 

-Daolin

Hi,

Thank you for your reply!

1.I checked the part you mentioned again. The corresponding PHY address of ETH0 network port is 1, and the PHY address of ETH1 network port is 0. I modified this part, but ETH1 still cannot be pinged. Like this.

&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};

cpsw3g_phy1: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};

2.Regarding your question 2, I set the IP address of ETH0 to 192.168.2.16 and the IP address of ETH1 to 192.168.1.166. At this time, ETH1 can still be pinged, but ETH0 cannot be pinged. During the whole process, I did not connect to the switch. I used the PC port to directly connect to the Ethernet port to be pinged, and only connected one at a time.

3.After using the ifconfig command, the following is displayed: there is sending but no receiving

eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 metric 1
inet 192.168.2.16 netmask 255.255.255.0 broadcast 192.168.2.255
inet6 fe80::3608:e1ff:fe84:ad17 prefixlen 64 scopeid 0x20<link>
ether 34:08:e1:84:ad:17 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 37 bytes 4776 (4.6 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

I uploaded the modified device tree file. Can you help me confirm the problem? Thank you very much.

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"

/ {
	compatible =  "ti,am642-evm", "ti,am642";
	model = "Texas Instruments AM642 EVM";

	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

	aliases {
		ethernet0 = &cpsw_port1;
		ethernet1 = &cpsw_port2;
		ethernet3 = &icssg0_emac0;
	};
	memory@80000000 {
		device_type = "memory";
		/* 2G RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;

	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
			alignment = <0x1000>;
			no-map;
		};

		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3100000 0x00 0xf00000>;
			no-map;
		};

		mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4000000 0x00 0x100000>;
			no-map;
		};

		mcu_m4fss_memory_region: m4f-memory@a4100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4100000 0x00 0xf00000>;
			no-map;
		};

		rtos_ipc_memory_region: ipc-memories@a5000000 {
			reg = <0x00 0xa5000000 0x00 0x00800000>;
			alignment = <0x1000>;
			no-map;
		};
	};

	transceiver1: can-phy0 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
	};
	
	transceiver2: can-phy1 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
	};

	icssg0_eth: icssg0-eth {
		compatible = "ti,am642-icssg-prueth";
		pinctrl-names = "default";
		pinctrl-0 = <&pru_icssg0_mii_g_rt_pins_default>;

		sram = <&oc_sram>;
		ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
		firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
				"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
				"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
				"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
				"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
				"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";

		ti,pruss-gp-mux-sel = <2>,	/* MII mode */
				      <2>,
				      <2>,
				      <2>,	/* MII mode */
				      <2>,
				      <2>;

		mii-g-rt = <&icssg0_mii_g_rt>;
		mii-rt = <&icssg0_mii_rt>;
		iep = <&icssg0_iep0>,  <&icssg0_iep1>;

		interrupt-parent = <&icssg0_intc>;
		interrupts = <24 0 2>, <25 1 3>;
		interrupt-names = "tx_ts0", "tx_ts1";

		dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
		       <&main_pktdma 0xc101 15>, /* egress slice 0 */
		       <&main_pktdma 0xc102 15>, /* egress slice 0 */
		       <&main_pktdma 0xc103 15>, /* egress slice 0 */
		       <&main_pktdma 0xc104 15>, /* egress slice 1 */
		       <&main_pktdma 0xc105 15>, /* egress slice 1 */
		       <&main_pktdma 0xc106 15>, /* egress slice 1 */
		       <&main_pktdma 0xc107 15>, /* egress slice 1 */
		       <&main_pktdma 0x4100 15>, /* ingress slice 0 */
		       <&main_pktdma 0x4101 15>, /* ingress slice 1 */
		       <&main_pktdma 0x4102 0>, /* mgmnt rsp slice 0 */
		       <&main_pktdma 0x4103 0>; /* mgmnt rsp slice 1 */
		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
			    "tx1-0", "tx1-1", "tx1-2", "tx1-3",
			    "rx0", "rx1",
			    "rxmgm0", "rxmgm1";

			icssg0_emac0: ethernet-mii0 {
				phy-handle = <&icssg0_phy0>;
				phy-mode = "mii";
				/*ti,syscon-rgmii-delay = <&main_conf 0x4110>;*/
				/* Filled in by bootloader */
				local-mac-address = [00 00 00 00 00 00];
		};
		icssg0_emac1: ethernet-mii1 {
			status = "disabled";
		};
	};
};
&main_r5fss0_core0 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
	memory-region = <&main_r5fss0_core0_dma_memory_region>,
			<&main_r5fss0_core0_memory_region>;
};

&main_r5fss0_core1 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
	memory-region = <&main_r5fss0_core1_dma_memory_region>,
			<&main_r5fss0_core1_memory_region>;
};

&main_r5fss1_core0 {
	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
	memory-region = <&main_r5fss1_core0_dma_memory_region>,
			<&main_r5fss1_core0_memory_region>;
};

&main_r5fss1_core1 {
	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
	memory-region = <&main_r5fss1_core1_dma_memory_region>,
			<&main_r5fss1_core1_memory_region>;
};

&mcu_m4fss {
	mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
	memory-region = <&mcu_m4fss_dma_memory_region>,
			<&mcu_m4fss_memory_region>;
};

&main_pmx0 {
	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
			AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
			AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
			AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
			AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
			AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
			AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
		>;
	};

	main_uart0_pins_default: main-uart0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
		>;
	};

	main_uart1_pins_default: main-uart1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
			AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
			AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
			AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
		>;
	};
	
	main_uart2_pins_default: main-uart2-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0238, PIN_INPUT, 3) /* (B16) UART2_RXD  UART0_CTSn*/
			AM64X_IOPAD(0x023c, PIN_OUTPUT, 3) /* (A16) UART2_TXD  UART0_RTSn*/
		>;
	};

	
//	main_uart4_pins_default: main-uart4-pins-default {
//		pinctrl-single,pins = <
//			AM64X_IOPAD(0x01DC, PIN_INPUT, 10) /* (W4) UART4_RXD  PRG0_PRU1_GPO11*/
//			AM64X_IOPAD(0x01cc, PIN_OUTPUT, 10) /* (W5) UART4_TXD  PRG0_PRU1_GPO7*/
//		>;
//	};

//	main_uart5_pins_default: main-uart5-pins-default {
//		pinctrl-single,pins = <
//			AM64X_IOPAD(0x01E4, PIN_INPUT, 10) /* (T6) UART5_RXD  PRG0_PRU1_GPO13*/
//			AM64X_IOPAD(0x01B4, PIN_OUTPUT, 10) /* (W2) UART5_TXD  PRG0_PRU1_GPO1*/
//		>;
//	};

//	main_uart6_pins_default: main-uart6-pins-default {
//		pinctrl-single,pins = <
//			AM64X_IOPAD(0x01E8, PIN_INPUT, 10) /* (U6) UART6_RXD  PRG0_PRU1_GPO14*/
//			AM64X_IOPAD(0x01C0, PIN_OUTPUT, 10) /* (W3) UART6_TXD  PRG0_PRU1_GPO4*/
//		>;
//	};
	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C1_SCL */
			AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C1_SDA */
		>;
	};

	mdio1_pins_default: mdio1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
		>;
	};

	di_do_pins_default: di_do_pins_default {
		pinctrl-single,pins = <
//			AM64X_IOPAD(0x01E0, PIN_OUTPUT, 7) /* (Y4) PRG0_PRU1_GPO12 GPIO1_32 */
//			AM64X_IOPAD(0x01D8, PIN_OUTPUT, 7) /* (V6) PRG0_PRU1_GPO10 GPIO1_30 */
//			AM64X_IOPAD(0x01D4, PIN_OUTPUT, 7) /* (Y5) PRG0_PRU1_GPO9 GPIO1_29 */
			AM64X_IOPAD(0x01D0, PIN_OUTPUT, 7) /* (R1) PRG0_PRU1_GPO8 GPIO1_28 */
			
			AM64X_IOPAD(0x01A4, PIN_INPUT, 7) /* (U1) PRG0_PRU0_GPO17 GPIO1_17 */
			AM64X_IOPAD(0x01A8, PIN_INPUT, 7) /* (V1) PRG0_PRU0_GPO18 GPIO1_18 */
			AM64X_IOPAD(0x017C, PIN_INPUT, 7) /* (T1) PRG0_PRU0_GPO7  GPIO1_7 */			
//			AM64X_IOPAD(0x01B8, PIN_INPUT, 7) /* (V3) PRG0_PRU1_GPO2  GPIO1_22 */	

		>;
	};
	
	rgmii1_pins_default: rgmii1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
			AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
			AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
			AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
			AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
			AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
		>;
	};

       rgmii2_pins_default: rgmii2-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
		>;
	};

	icssg0_mdio0_pins_default: icssg0_mdio_pins_default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */
			AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */
		>;
	};

	pru_icssg0_mii_g_rt_pins_default: pru_icssg0_mii_g_rt_pins_default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x01a0, PIN_INPUT, 1) /* (U4) PRG0_PRU0_GPO16.PR0_MII_MT0_CLK */
			AM64X_IOPAD(0x019c, PIN_OUTPUT, 0) /* (T5) PRG0_PRU0_GPO15.PR0_MII0_TXEN */
			AM64X_IOPAD(0x0198, PIN_OUTPUT, 0) /* (V4) PRG0_PRU0_GPO14.PR0_MII0_TXD3 */
			AM64X_IOPAD(0x0194, PIN_OUTPUT, 0) /* (R6) PRG0_PRU0_GPO13.PR0_MII0_TXD2 */
			AM64X_IOPAD(0x0190, PIN_OUTPUT, 0) /* (AA3) PRG0_PRU0_GPO12.PR0_MII0_TXD1 */
			AM64X_IOPAD(0x018c, PIN_OUTPUT, 0) /* (Y3) PRG0_PRU0_GPO11.PR0_MII0_TXD0 */
			AM64X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA2) PRG0_PRU0_GPO4.PR0_MII0_RXDV */
			AM64X_IOPAD(0x0178, PIN_INPUT, 1) /* (T3) PRG0_PRU0_GPO6.PR0_MII_MR0_CLK */
			AM64X_IOPAD(0x016c, PIN_INPUT, 1) /* (V2) PRG0_PRU0_GPO3.PR0_MII0_RXD3 */
			AM64X_IOPAD(0x0168, PIN_INPUT, 1) /* (U2) PRG0_PRU0_GPO2.PR0_MII0_RXD2 */
			AM64X_IOPAD(0x0188, PIN_INPUT, 1) /* (AA5) PRG0_PRU0_GPO10.PR0_MII0_CRS */
			AM64X_IOPAD(0x0174, PIN_INPUT, 1) /* (R3) PRG0_PRU0_GPO5.PR0_MII0_RXER */
			AM64X_IOPAD(0x0164, PIN_INPUT, 1) /* (R4) PRG0_PRU0_GPO1.PR0_MII0_RXD1 */
			AM64X_IOPAD(0x0160, PIN_INPUT, 1) /* (Y1) PRG0_PRU0_GPO0.PR0_MII0_RXD0 */
			AM64X_IOPAD(0x0184, PIN_INPUT, 1) /* (W6) PRG0_PRU0_GPO9.PR0_MII0_COL */
						
			AM64X_IOPAD(0x01f0, PIN_INPUT, 1) /* (AA4) PRG0_PRU1_GPO16.PR0_MII_MT1_CLK */
			AM64X_IOPAD(0x01ec, PIN_OUTPUT, 0) /* (U5) PRG0_PRU1_GPO15.PR0_MII1_TXEN */
			AM64X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (U6) PRG0_PRU1_GPO14.PR0_MII1_TXD3 */
			AM64X_IOPAD(0x01e4, PIN_OUTPUT, 0) /* (T6) PRG0_PRU1_GPO13.PR0_MII1_TXD2 */
			AM64X_IOPAD(0x01e0, PIN_OUTPUT, 0) /* (Y4) PRG0_PRU1_GPO12.PR0_MII1_TXD1 */
			AM64X_IOPAD(0x01dc, PIN_OUTPUT, 0) /* (W4) PRG0_PRU1_GPO11.PR0_MII1_TXD0 */
			AM64X_IOPAD(0x01c0, PIN_INPUT, 1) /* (W3) PRG0_PRU1_GPO4.PR0_MII1_RXDV */
			AM64X_IOPAD(0x01c8, PIN_INPUT, 1) /* (R5) PRG0_PRU1_GPO6.PR0_MII_MR1_CLK */
			AM64X_IOPAD(0x01bc, PIN_INPUT, 1) /* (T4) PRG0_PRU1_GPO3.PR0_MII1_RXD3 */
			AM64X_IOPAD(0x01b8, PIN_INPUT, 1) /* (V3) PRG0_PRU1_GPO2.PR0_MII1_RXD2 */
			AM64X_IOPAD(0x01d8, PIN_INPUT, 1) /* (V6) PRG0_PRU1_GPO10.PR0_MII1_CRS */
			AM64X_IOPAD(0x01c4, PIN_INPUT, 1) /* (P4) PRG0_PRU1_GPO5.PR0_MII1_RXER */
			AM64X_IOPAD(0x01b4, PIN_INPUT, 1) /* (W2) PRG0_PRU1_GPO1.PR0_MII1_RXD1 */
			AM64X_IOPAD(0x01b0, PIN_INPUT, 1) /* (Y2) PRG0_PRU1_GPO0.PR0_MII1_RXD0 */
			AM64X_IOPAD(0x01d4, PIN_INPUT, 1) /* (Y5) PRG0_PRU1_GPO9.PR0_MII1_COL */
		>;
	}; 
	
	ospi0_pins_default: ospi0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
		>;
	};

	main_mcan0_pins_default: main-mcan0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
			AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
		>;
	};
	
	main_mcan1_pins_default: main-mcan1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
			AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
		>;
	};

};

&main_gpio1 {
	pinctrl-names = "default";
	pinctrl-0 = <&di_do_pins_default>;
	status = "okay";
};

&main_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
};

/* main_uart1 is reserved for firmware usage */
&main_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart1_pins_default>;
};

&main_uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart2_pins_default>;
};

&main_uart3 {
		status = "disabled";
};

&main_uart4 {
//	pinctrl-names = "default";
//	pinctrl-0 = <&main_uart4_pins_default>;
	status = "disabled";
};

&main_uart5 {
//	pinctrl-names = "default";
//	pinctrl-0 = <&main_uart5_pins_default>;
status = "disabled";
};

&main_uart6 {
//	pinctrl-names = "default";
//	pinctrl-0 = <&main_uart6_pins_default>;
		status = "disabled";
};

&mcu_uart0 {
	status = "disabled";
};

&mcu_uart1 {
	status = "disabled";
};

&main_i2c1 {
	status = "disabled";

};

/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
	status = "reserved";
};

&mcu_i2c0 {
	status = "disabled";
};

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;
};
&mcu_i2c1 {
	status = "disabled";
};

&mcu_spi0 {
	status = "disabled";
};

&mcu_spi1 {
	status = "disabled";
};

&main_spi0 {
	status = "disabled";
};

&sdhci0 {
	/* emmc */
	bus-width = <8>;
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&sdhci1 {
	/* SD/MMC */
	pinctrl-names = "default";
	bus-width = <4>;
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	no-1-8-v;
};


&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio1_pins_default
		     &rgmii1_pins_default
		     &rgmii2_pins_default>;
		cpts@3d000 {
		ti,pps = <7 1>;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy0>;
};

&cpsw_port2 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy1>;
};

&cpsw3g_mdio {
	cpsw3g_phy0: ethernet-phy@1 {
		reg = <1>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};

	cpsw3g_phy1: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};
};

#define TS_OFFSET(pa, val)     (0x4+(pa)*4) (0x10000 | val)

&timesync_router {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpts_pps>;

	/* Example of the timesync routing */
	mcu_cpts_pps: mcu-cpts-pps {
		pinctrl-single,pins = <
				/* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */
				TS_OFFSET(37, 22)
				/* pps [cpts genf1] in22 -> out25 [SYNC1_OUT pin] */
				TS_OFFSET(25, 22)
				>;
	};
};

&mailbox0_cluster2 {
	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};

	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
		ti,mbox-rx = <2 0 2>;
		ti,mbox-tx = <3 0 2>;
	};
};

&mailbox0_cluster3 {
	status = "disabled";
};

&mailbox0_cluster4 {
	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};

	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
		ti,mbox-rx = <2 0 2>;
		ti,mbox-tx = <3 0 2>;
	};
};

&mailbox0_cluster5 {
	status = "disabled";
};

&mailbox0_cluster6 {
	mbox_m4_0: mbox-m4-0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};
};

&mailbox0_cluster7 {
	status = "disabled";
};

&serdes_ln_ctrl {
	idle-states = <AM64_SERDES0_LANE0_PCIE0>;
};

&serdes0 {
	status = "disabled";
};

&pcie0_rc {
	status = "disabled";
};

&pcie0_ep {
	status = "disabled";
};

&tscadc0 {
	/* ADC is reserved for R5 usage */
	status = "reserved";
};

&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;

	flash@0{
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <4>;
		cdns,phy-mode;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

&main_mcan0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan0_pins_default>;
	phys = <&transceiver1>;
};

&main_mcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan1_pins_default>;
	phys = <&transceiver2>;
};

&icssg0_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&icssg0_mdio0_pins_default>;

	icssg0_phy0: ethernet-phy@3 {
		reg = <0x3>;
		tx-internal-delay-ps = <250>;
		rx-internal-delay-ps = <2000>;
	};
//	icssg0_phy1: ethernet-phy@4 {
//		reg = <0x4>;
//		tx-internal-delay-ps = <250>;
//		rx-internal-delay-ps = <2000>;
//	};
};

&icssg1_mdio {
	status = "disabled";
};

Hello,

Wendy said:

The corresponding PHY address of ETH0 network port is 1, and the PHY address of ETH1 network port is 0. I modified this part, but ETH1 still cannot be pinged

Thanks for clarifying, in this case, since your hardware has PHY address connected to eth0 is 1 and PHY address connected to eth1 is 0, your previous configuration for the cpsw3g_phy nodes seems to be correct. I checked over the other cpsw nodes in your device tree and nothing else seems to be out of the ordinary (as long as you are using DP83867 PHYs for both ethernet interfaces).

Wendy said:

IP address of ETH0 to 192.168.2.16 and the IP address of ETH1 to 192.168.1.166. At this time, ETH1 can still be pinged, but ETH0 cannot be pinged. During the whole process, I did not connect to the switch. I used the PC port to directly connect to the Ethernet port to be pinged, and only connected one at a time.

What is the IP address of the PC port? If the IP address of the PC port was configured for the same subnet as eth1 interface, then it would make sense why eth1 can ping but eth0 cannot ping, especially since you are testing each port one at a time. In this case, eth0 would not be able to ping since the subnet of eth0 is different from the PC port. What I stated in my previous response is only really relevant when both ports are connected to the host PC at the same time and are on the same subnet. 

Wendy said:

After using the ifconfig command, the following is displayed: there is sending but no receiving

Since you are able to display ifconfig, can you similarly show the results of "ethtool -S eth0" and "ethtool -S eth1" after ping from your DUT. Additionally, if your host PC is running Linux, can you also share the ethtool -S outputs on the PC after the ping?

-Daolin

Hi,

1.The PHY I am using is DP83867.

2.When connected to ETH0, the IP address of the PC port  is set to 192.168.2.253, and when connected to ETH1, the IP address of the PC port is set to 192.168.1.253。

3.My host PC is  not running Linux,l post the information that might be useful.

1.
root@am64xx-evm:~# ethtool -S eth0
NIC statistics:
     p0_rx_good_frames: 17
     p0_rx_broadcast_frames: 6
     p0_rx_multicast_frames: 11
     p0_rx_crc_errors: 0
     p0_rx_oversized_frames: 0
     p0_rx_undersized_frames: 0
     p0_ale_drop: 0
     p0_ale_overrun_drop: 0
     p0_rx_octets: 1548
     p0_tx_good_frames: 0
     p0_tx_broadcast_frames: 0
     p0_tx_multicast_frames: 0
     p0_tx_octets: 0
     p0_tx_64B_frames: 6
     p0_tx_65_to_127B_frames: 5
     p0_tx_128_to_255B_frames: 6
     p0_tx_256_to_511B_frames: 0
     p0_tx_512_to_1023B_frames: 0
     p0_tx_1024B_frames: 0
     p0_net_octets: 1548
     p0_rx_bottom_fifo_drop: 0
     p0_rx_port_mask_drop: 0
     p0_rx_top_fifo_drop: 0
     p0_ale_rate_limit_drop: 0
     p0_ale_vid_ingress_drop: 0
     p0_ale_da_eq_sa_drop: 0
     p0_ale_block_drop: 0
     p0_ale_secure_drop: 0
     p0_ale_auth_drop: 0
     p0_ale_unknown_ucast: 0
     p0_ale_unknown_ucast_bytes: 0
     p0_ale_unknown_mcast: 0
     p0_ale_unknown_mcast_bytes: 0
     p0_ale_unknown_bcast: 0
     p0_ale_unknown_bcast_bytes: 0
     p0_ale_pol_match: 0
     p0_ale_pol_match_red: 0
     p0_ale_pol_match_yellow: 0
     p0_ale_mcast_sa_drop: 0
     p0_ale_dual_vlan_drop: 0
     p0_ale_len_err_drop: 0
     p0_ale_ip_next_hdr_drop: 0
     p0_ale_ipv4_frag_drop: 0
     p0_tx_mem_protect_err: 0
     p0_tx_pri0: 0
     p0_tx_pri1: 0
     p0_tx_pri2: 0
     p0_tx_pri3: 0
     p0_tx_pri4: 0
     p0_tx_pri5: 0
     p0_tx_pri6: 0
     p0_tx_pri7: 0
     p0_tx_pri0_bcnt: 0
     p0_tx_pri1_bcnt: 0
     p0_tx_pri2_bcnt: 0
     p0_tx_pri3_bcnt: 0
     p0_tx_pri4_bcnt: 0
     p0_tx_pri5_bcnt: 0
     p0_tx_pri6_bcnt: 0
     p0_tx_pri7_bcnt: 0
     p0_tx_pri0_drop: 0
     p0_tx_pri1_drop: 0
     p0_tx_pri2_drop: 0
     p0_tx_pri3_drop: 0
     p0_tx_pri4_drop: 0
     p0_tx_pri5_drop: 0
     p0_tx_pri6_drop: 0
     p0_tx_pri7_drop: 0
     p0_tx_pri0_drop_bcnt: 0
     p0_tx_pri1_drop_bcnt: 0
     p0_tx_pri2_drop_bcnt: 0
     p0_tx_pri3_drop_bcnt: 0
     p0_tx_pri4_drop_bcnt: 0
     p0_tx_pri5_drop_bcnt: 0
     p0_tx_pri6_drop_bcnt: 0
     p0_tx_pri7_drop_bcnt: 0
     rx_good_frames: 0
     rx_broadcast_frames: 0
     rx_multicast_frames: 0
     rx_pause_frames: 0
     rx_crc_errors: 0
     rx_align_code_errors: 0
     rx_oversized_frames: 0
     rx_jabber_frames: 0
     rx_undersized_frames: 0
     rx_fragments: 0
     ale_drop: 0
     ale_overrun_drop: 0
     rx_octets: 0
     tx_good_frames: 17
     tx_broadcast_frames: 6
     tx_multicast_frames: 11
     tx_pause_frames: 0
     tx_deferred_frames: 0
     tx_collision_frames: 0
     tx_single_coll_frames: 0
     tx_mult_coll_frames: 0
     tx_excessive_collisions: 0
     tx_late_collisions: 0
     rx_ipg_error: 0
     tx_carrier_sense_errors: 0
     tx_octets: 1548
     tx_64B_frames: 6
     tx_65_to_127B_frames: 5
     tx_128_to_255B_frames: 6
     tx_256_to_511B_frames: 0
     tx_512_to_1023B_frames: 0
     tx_1024B_frames: 0
     net_octets: 1548
     rx_bottom_fifo_drop: 0
     rx_port_mask_drop: 0
     rx_top_fifo_drop: 0
     ale_rate_limit_drop: 0
     ale_vid_ingress_drop: 0
     ale_da_eq_sa_drop: 0
     ale_block_drop: 0
     ale_secure_drop: 0
     ale_auth_drop: 0
     ale_unknown_ucast: 0
     ale_unknown_ucast_bytes: 0
     ale_unknown_mcast: 0
     ale_unknown_mcast_bytes: 0
     ale_unknown_bcast: 0
     ale_unknown_bcast_bytes: 0
     ale_pol_match: 0
     ale_pol_match_red: 0
     ale_pol_match_yellow: 0
     ale_mcast_sa_drop: 0
     ale_dual_vlan_drop: 0
     ale_len_err_drop: 0
     ale_ip_next_hdr_drop: 0
     ale_ipv4_frag_drop: 0
     iet_rx_assembly_err: 0
     iet_rx_assembly_ok: 0
     iet_rx_smd_err: 0
     iet_rx_frag: 0
     iet_tx_hold: 0
     iet_tx_frag: 0
     tx_mem_protect_err: 0
     tx_pri0: 17
     tx_pri1: 0
     tx_pri2: 0
     tx_pri3: 0
     tx_pri4: 0
     tx_pri5: 0
     tx_pri6: 0
     tx_pri7: 0
     tx_pri0_bcnt: 1548
     tx_pri1_bcnt: 0
     tx_pri2_bcnt: 0
     tx_pri3_bcnt: 0
     tx_pri4_bcnt: 0
     tx_pri5_bcnt: 0
     tx_pri6_bcnt: 0
     tx_pri7_bcnt: 0
     tx_pri0_drop: 0
     tx_pri1_drop: 0
     tx_pri2_drop: 0
     tx_pri3_drop: 0
     tx_pri4_drop: 0
     tx_pri5_drop: 0
     tx_pri6_drop: 0
     tx_pri7_drop: 0
     tx_pri0_drop_bcnt: 0
     tx_pri1_drop_bcnt: 0
     tx_pri2_drop_bcnt: 0
     tx_pri3_drop_bcnt: 0
     tx_pri4_drop_bcnt: 0
     tx_pri5_drop_bcnt: 0
     tx_pri6_drop_bcnt: 0
     tx_pri7_drop_bcnt: 0


2.root@am64xx-evm:~# ethtool -S eth1
NIC statistics:
     p0_rx_good_frames: 34
     p0_rx_broadcast_frames: 6
     p0_rx_multicast_frames: 22
     p0_rx_crc_errors: 0
     p0_rx_oversized_frames: 0
     p0_rx_undersized_frames: 0
     p0_ale_drop: 0
     p0_ale_overrun_drop: 0
     p0_rx_octets: 3158
     p0_tx_good_frames: 76
     p0_tx_broadcast_frames: 34
     p0_tx_multicast_frames: 37
     p0_tx_octets: 6614
     p0_tx_64B_frames: 31
     p0_tx_65_to_127B_frames: 62
     p0_tx_128_to_255B_frames: 17
     p0_tx_256_to_511B_frames: 0
     p0_tx_512_to_1023B_frames: 0
     p0_tx_1024B_frames: 0
     p0_net_octets: 9772
     p0_rx_bottom_fifo_drop: 0
     p0_rx_port_mask_drop: 0
     p0_rx_top_fifo_drop: 0
     p0_ale_rate_limit_drop: 0
     p0_ale_vid_ingress_drop: 0
     p0_ale_da_eq_sa_drop: 0
     p0_ale_block_drop: 0
     p0_ale_secure_drop: 0
     p0_ale_auth_drop: 0
     p0_ale_unknown_ucast: 0
     p0_ale_unknown_ucast_bytes: 0
     p0_ale_unknown_mcast: 0
     p0_ale_unknown_mcast_bytes: 0
     p0_ale_unknown_bcast: 0
     p0_ale_unknown_bcast_bytes: 0
     p0_ale_pol_match: 0
     p0_ale_pol_match_red: 0
     p0_ale_pol_match_yellow: 0
     p0_ale_mcast_sa_drop: 0
     p0_ale_dual_vlan_drop: 0
     p0_ale_len_err_drop: 0
     p0_ale_ip_next_hdr_drop: 0
     p0_ale_ipv4_frag_drop: 0
     p0_tx_mem_protect_err: 0
     p0_tx_pri0: 76
     p0_tx_pri1: 0
     p0_tx_pri2: 0
     p0_tx_pri3: 0
     p0_tx_pri4: 0
     p0_tx_pri5: 0
     p0_tx_pri6: 0
     p0_tx_pri7: 0
     p0_tx_pri0_bcnt: 6614
     p0_tx_pri1_bcnt: 0
     p0_tx_pri2_bcnt: 0
     p0_tx_pri3_bcnt: 0
     p0_tx_pri4_bcnt: 0
     p0_tx_pri5_bcnt: 0
     p0_tx_pri6_bcnt: 0
     p0_tx_pri7_bcnt: 0
     p0_tx_pri0_drop: 0
     p0_tx_pri1_drop: 0
     p0_tx_pri2_drop: 0
     p0_tx_pri3_drop: 0
     p0_tx_pri4_drop: 0
     p0_tx_pri5_drop: 0
     p0_tx_pri6_drop: 0
     p0_tx_pri7_drop: 0
     p0_tx_pri0_drop_bcnt: 0
     p0_tx_pri1_drop_bcnt: 0
     p0_tx_pri2_drop_bcnt: 0
     p0_tx_pri3_drop_bcnt: 0
     p0_tx_pri4_drop_bcnt: 0
     p0_tx_pri5_drop_bcnt: 0
     p0_tx_pri6_drop_bcnt: 0
     p0_tx_pri7_drop_bcnt: 0
     rx_good_frames: 243
     rx_broadcast_frames: 34
     rx_multicast_frames: 204
     rx_pause_frames: 0
     rx_crc_errors: 0
     rx_align_code_errors: 0
     rx_oversized_frames: 0
     rx_jabber_frames: 0
     rx_undersized_frames: 0
     rx_fragments: 0
     ale_drop: 167
     ale_overrun_drop: 0
     rx_octets: 68872
     tx_good_frames: 17
     tx_broadcast_frames: 0
     tx_multicast_frames: 11
     tx_pause_frames: 0
     tx_deferred_frames: 0
     tx_collision_frames: 0
     tx_single_coll_frames: 0
     tx_mult_coll_frames: 0
     tx_excessive_collisions: 0
     tx_late_collisions: 0
     rx_ipg_error: 0
     tx_carrier_sense_errors: 0
     tx_octets: 1610
     tx_64B_frames: 37
     tx_65_to_127B_frames: 104
     tx_128_to_255B_frames: 57
     tx_256_to_511B_frames: 0
     tx_512_to_1023B_frames: 54
     tx_1024B_frames: 8
     net_octets: 70482
     rx_bottom_fifo_drop: 0
     rx_port_mask_drop: 167
     rx_top_fifo_drop: 0
     ale_rate_limit_drop: 0
     ale_vid_ingress_drop: 0
     ale_da_eq_sa_drop: 0
     ale_block_drop: 0
     ale_secure_drop: 0
     ale_auth_drop: 0
     ale_unknown_ucast: 5
     ale_unknown_ucast_bytes: 376
     ale_unknown_mcast: 204
     ale_unknown_mcast_bytes: 65624
     ale_unknown_bcast: 34
     ale_unknown_bcast_bytes: 2872
     ale_pol_match: 0
     ale_pol_match_red: 0
     ale_pol_match_yellow: 0
     ale_mcast_sa_drop: 0
     ale_dual_vlan_drop: 0
     ale_len_err_drop: 0
     ale_ip_next_hdr_drop: 0
     ale_ipv4_frag_drop: 0
     iet_rx_assembly_err: 0
     iet_rx_assembly_ok: 0
     iet_rx_smd_err: 0
     iet_rx_frag: 0
     iet_tx_hold: 0
     iet_tx_frag: 0
     tx_mem_protect_err: 0
     tx_pri0: 17
     tx_pri1: 0
     tx_pri2: 0
     tx_pri3: 0
     tx_pri4: 0
     tx_pri5: 0
     tx_pri6: 0
     tx_pri7: 0
     tx_pri0_bcnt: 1610
     tx_pri1_bcnt: 0
     tx_pri2_bcnt: 0
     tx_pri3_bcnt: 0
     tx_pri4_bcnt: 0
     tx_pri5_bcnt: 0
     tx_pri6_bcnt: 0
     tx_pri7_bcnt: 0
     tx_pri0_drop: 0
     tx_pri1_drop: 0
     tx_pri2_drop: 0
     tx_pri3_drop: 0
     tx_pri4_drop: 0
     tx_pri5_drop: 0
     tx_pri6_drop: 0
     tx_pri7_drop: 0
     tx_pri0_drop_bcnt: 0
     tx_pri1_drop_bcnt: 0
     tx_pri2_drop_bcnt: 0
     tx_pri3_drop_bcnt: 0
     tx_pri4_drop_bcnt: 0
     tx_pri5_drop_bcnt: 0
     tx_pri6_drop_bcnt: 0
     tx_pri7_drop_bcnt: 0
     
3.
root@am64xx-evm:~# ethtool eth0
Settings for eth0:
        Supported ports: [ TP    MII ]
        Supported link modes:   10baseT/Half 10baseT/Full
                                100baseT/Half 100baseT/Full
                                1000baseT/Full
        Supported pause frame use: Symmetric
        Supports auto-negotiation: Yes
        Supported FEC modes: Not reported
        Advertised link modes:  10baseT/Half 10baseT/Full
                                100baseT/Half 100baseT/Full
                                1000baseT/Full
        Advertised pause frame use: Symmetric
        Advertised auto-negotiation: Yes
        Advertised FEC modes: Not reported
        Link partner advertised link modes:  10baseT/Half 10baseT/Full
                                             100baseT/Half 100baseT/Full
        Link partner advertised pause frame use: Symmetric Receive-only
        Link partner advertised auto-negotiation: Yes
        Link partner advertised FEC modes: Not reported
        Speed: 100Mb/s
        Duplex: Full
        Auto-negotiation: on
        master-slave cfg: preferred slave
        master-slave status: slave
        Port: Twisted Pair
        PHYAD: 1
        Transceiver: external
        MDI-X: Unknown
        Supports Wake-on: ubgs
        Wake-on: d
        SecureOn password: 00:00:00:00:00:00
        Current message level: 0x000020f7 (8439)
                               drv probe link ifdown ifup rx_err tx_err hw
        Link detected: yes

4.
[    1.416753] davinci_mdio 8000f00.mdio: Configuring MDIO in manual mode
[    1.460860] davinci_mdio 8000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    1.471092] davinci_mdio 8000f00.mdio: phy[0]: device 8000f00.mdio:00, driver TI DP83867
[    1.479218] davinci_mdio 8000f00.mdio: phy[1]: device 8000f00.mdio:01, driver TI DP83867
[    1.487423] am65-cpsw-nuss 8000000.ethernet: initializing am65 cpsw nuss version 0x6BA00903, cpsw version 0x6BA80903 Ports: 3 quirks:00000006
[    1.500406] am65-cpsw-nuss 8000000.ethernet: Use random MAC address
[    1.506681] am65-cpsw-nuss 8000000.ethernet: initialized cpsw ale version 1.4
[    1.513808] am65-cpsw-nuss 8000000.ethernet: ALE Table size 512
[    1.520519] pps pps0: new PPS source ptp0
[    1.524985] am65-cpsw-nuss 8000000.ethernet: CPTS ver 0x4e8a010c, freq:500000000, add_val:1 pps:1
[    1.535645] am65-cpsw-nuss 8000000.ethernet: set new flow-id-base 16

[    9.484623] am65-cpsw-nuss 8000000.ethernet eth1: PHY [8000f00.mdio:00] driver [TI DP83867] (irq=POLL)
[    9.537033] am65-cpsw-nuss 8000000.ethernet eth1: configuring for phy/rgmii-rxid link mode
[    9.654112] am65-cpsw-nuss 8000000.ethernet eth0: PHY [8000f00.mdio:01] driver [TI DP83867] (irq=POLL)
[    9.669756] am65-cpsw-nuss 8000000.ethernet eth0: configuring for phy/rgmii-rxid link mode

Hi，

I have found the problem.Find the corresponding 642evm.dts file in uboot. Only one CPSW network port is used in it. After adding the second network port in this part, the ETH0 network port can be pinged normally.What I do not understand is that even if the second network port is not defined in the device tree in uboot, the network port should be driven according to the device tree file in the kernel after entering the kernel. Why is it not what I think?

I have another question.The following information is printed when it is just started. How can I modify this part? If the board identification is not specially defined, will it be processed as GP-EVM? Where is this part implemented?

EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1

Failed to load 'boot.scr'

Hello,

Wendy said:

I have found the problem.Find the corresponding 642evm.dts file in uboot. Only one CPSW network port is used in it. After adding the second network port in this part, the ETH0 network port can be pinged normally.

Thanks for sharing this finding! May I ask how you thought of trying to modify the dts for u-boot?

Wendy said:

What I do not understand is that even if the second network port is not defined in the device tree in uboot, the network port should be driven according to the device tree file in the kernel after entering the kernel. Why is it not what I think?

I agree with your statement that typically only changes in the kernel device tree file should configure peripherals in the kernel. However, as mentioned before, it appears that you are using PHY at address 0 to eth1 (RGMII2) and PHY at address 1 to eth0 (RGMII1). This appears to be a flipped port design similar to this other E2E thread where they were experiencing similar behavior of only one interface able to ping: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1383477/am6422-flip-rgmii-ports-on-am64x/5304275. 

I will need to check with a colleague and the developer on why enabling the 2nd port in u-boot device tree will enable both ethernet interfaces to ping. I hope to respond with an update next week.

Wendy said:

I have another question.The following information is printed when it is just started. How can I modify this part? If the board identification is not specially defined, will it be processed as GP-EVM? Where is this part implemented?

EEPROM not available at 80, trying to read at 81
Reading on-board EEPROM at 0x51 failed -1

Since this is more of a U-boot/EEPROM question, not directly related to ethernet, I suggest creating a separate E2E post as that will be the fastest way to get an expert on U-boot to respond to this inquiry.

-Daolin

Daolin Qiu said:

I will need to check with a colleague and the developer on why enabling the 2nd port in u-boot device tree will enable both ethernet interfaces to ping. I hope to respond with an update next week.

Could it be that the Ethernet PHY for the 2nd port is still held in reset so that ping communication won't occur while in Linux environment? The feedback I'm getting is that it could be that enabling the 2nd port in u-boot ensures that the PHY is not left in reset. Again, this could be due to the flipped port hardware configuration on your platform.

-Daolin

Hello,

I do not think this is the reason. I use CPSW Ethernet, eth0 is defined by default in uboot, and eth1 is configured in the kernel device tree. Without modifying uboot, eth0 cannot be pinged, but eth1 works normally. I also confirmed the reset pin of PHY, and it is not always in reset state. Is there any other reason?

Hello,

I just want to double check, you mentioned eth1 cannot be pinged first but later mention that eth0 cannot be pinged. Just to make sure I'm understanding, eth1 can ping all the time, it's just eth0 that has issues?

Wendy said:

The corresponding PHY address of ETH0 network port is 1, and the PHY address of ETH1 network port is 0. I modified this part, but ETH1 still cannot be pinged

Wendy said:

Regarding your question 2, I set the IP address of ETH0 to 192.168.2.16 and the IP address of ETH1 to 192.168.1.166. At this time, ETH1 can still be pinged, but ETH0 cannot be pinged.

Have you tried checking the u-boot device tree file that the pinmuxing and the PHY address is configured to the same flipped port address you had in your Kernel device tree file for eth0 port? (i.e. eth0 has PHY address 1 instead of PHY address 0)?

Wendy said:

eth0 is defined by default in uboot

-Daolin

Hi，

I have been talking about eth0 can not ping.I checked the device tree file of uboot, and the default PHY address is inconsistent with what I use.My question is that no matter what uboot is configured, after the kernel is running, it will be reconfigured according to the kernel device tree. Why can not this work properly? What is the role of the device tree file in uboot?The following is a comparison between before and after the modification.

uboot  old

uboot  modfied

Hello,

I am sorry for the following content. I wrote the wrong eth name, which led to giving you wrong information.

"The corresponding PHY address of ETH0 network port is 1, and the PHY address of ETH1 network port is 0. I modified this part, but ETH1 still cannot be pinged".

The problem is always eth0.