Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
We have a register in the MCU domain timers, called TOWR, responsible for masking overflow ticks. If you set it to 10, only the 10th timer overflow will count as effective, from what I understand, so, in short, the timer can overflow as many times as I think necessary and only count as a legitimate overflow when I want. My question is: if my timer is configured for the "one pulse mode" parameter, would the timer reset the number of interruptions required by TOWR at each stop and new trigger or would it continue counting, regardless of whether its state in the TCLR is reset?
I have already tested TOWR and it works perfectly, however, I do not have my setup to test this hypothesis about onepulse. I want to connect a pulse generator, which will have a physical output, pwm mode, as a cascade to another timer, which will be triggered at each pulse, counting from 0xFFFFFFFD to 0xFFFFFFFF and stopping, thus requiring one pulse. It will mask all events until a specific number of trigger pulses is reached, basically, working as a pulse counter, but without needing to interrupt due to match or overflow. It will only trigger my irq function when it reaches the number of pulses that I determine.
