DRA829J: MCSPI reference clock, valid range

Hi Tarun,

unfortunately 25MHz might be too slow for us and 50MHz is too fast for the MRAM connected to MCSPI. So we would need to have 40MHz.

Theoretically can I source MCSPI with 80/120/160MHz or is there any limitations for the reference clock?

Thanks,
Dmitry

Hello,

May i know which instance of SPI you are planning to use ?

Regards

Tarun Mukesh

Hello Tarun,

all main MCSPI instances will be utilized.

Hello,

To all Main McSPI instances MAIN_PLL0_HSDIV5 as SPI functional clock and it is fixed at 50MHz. I have asked HW expert whether we can change the PLL even though its fixed or not.Waiting for his feedback , i shall reply you accordingly.

Regards

Tarun Mukesh

Thank you Tarun, looking forward to hearing from you.

Hello,

Thanks for understanding.Meanwhile can you try changing HSDIV value in below register and see you are facing any issues

1. Unlock the MMR.

2. Update the value of HSDIV from 19 to 24

Regards

Tarun MUkesh

Hello Tarun,

thank you for the inputs.

Do you know if there are any limitations in terms of clock value used to source MCSPI? I mean can we reduce HSDIV, not to increase.

For example can we force input of 80/120MHz and then divide it down by internal MCSPI divider?

I know how to do it technically, the main question if MCSPI works stable with higher input clocks (e.g. reference clock is 120MHz and internal diviser of 3 or 4).

Thanks,
Dmitry

Hello,

As far as i know we cannot force the input to higher levels of clocks it might fail. As i told i requested support from HW expert on this.

Regards

Tarun Mukesh

Hello Tarun,

is there any update on the topic?

On our side we preliminary want to stick to ~144MHz inputs clock, if there are no limitations on HW side, of course.

Thanks,
Dmitry

Hello Tarun,

you answered all my questions, thank you.

Topic can be closed.

Regards,
Dmitry