AM623: About the configuration of spi DMA host mode

Hello Bu,

Thanks for your question.

I read through your question and got the following understanding:

1. You want to use nuclear spi > can you explain what nuclear is here ? 
2. Also you want to use nuclear spi as the controller? Is that correct understanding?

3. What do you mean by fpga as the spi from the machine, do you mean to say that you would treat fpga as a SPI module ? 

Regards,

Vaibhav

I use spi0 of CPU A core as the host, which is connected to fpga, and fpga as the spi slave. Then I hope to realize the cooperation mode similar to SPI+DMA+FIFO+IRQ, in which fpga sends data to fifo, and dma sends data from fifo to memory. Would like to ask whether the current kernel dma has this part of the driver, how to configure?

I use spi0 of CPU A core as the host, which is connected to fpga, and fpga as the spi slave. Then I hope to realize the cooperation mode similar to SPI+DMA+FIFO+IRQ, in which fpga sends data to fifo, and dma sends data from fifo to memory. Would like to ask whether the current kernel dma has this part of the driver, how to configure?

Hello Bu,

Thanks for your detailed explanation.

I will go ahead and assign your question to another expert, please expect responses in sometime.

Regards,

Vaibhav

Hi Bu,

this looks like a duplicate of your earlier question (where an answer was provided too) at https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1381318/am623-how-to-configure-the-main_spi0-of-am623-as-the-host-and-the-fpga-as-the-slave-and-configure-the-main_spi0-of-am623-as-the-dma-mode-and-configure-the-passive-receiving-mode-to-actively-read-the-data-of-the-fpga-buffer-th/5280646#5280646

What else do you need to get started?

Regards, Andreas

I want to know if CPU core A is the SPI host and fpga is the SPI slave. I configure dma to realize that fpga keeps sending data, and dma automatically receives and moves it to memory. In this process, cpu does not need to participate, because cpu is too slow to participate in reading. And whether dma has the configuration and related drivers for this mode

So what you want is for an external interrupt to automatically trigger the DMA to transfer data from the FPGA to the AM62?
What are your throughput/latency requirements that this is needed?

Even if you get this piece working you'll still need to process the data on the AM62 side for which you'll need to use software. So I want to understand the thought process of trying to optimize this specific piece.

Regards, Andreas

I want to reach 20ms 128*32 byte

Now I encounter the problem is that the CPU A core does not have a slave driver, using the host mode to read data through spi is too slow, so I plan to not let the CPU participate in this process, let the fpga and DMA directly for data transmission, so I want to know whether the current configuration and driver of this mode

bu yuying said:

I want to reach 20ms 128*32 byte

So that sounds like in average you transfer about 200KB/s? That doesn't sound too bad I think. If you configure for a SPI CLK speed of 10MHz (or 25MHz) and do some optimizations as suggested earlier (https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1356551/faq-am6x-optimizing-spi-transfer-inter-byte-gaps-using-the-dma-in-linux) that throughput should be achievable, still allowing a couple of ms for any interrupt-caused latencies. Have you tried experimenting with this? This being said a custom driver that combines SPI master + interrupt trigger based on existing kernel drivers as suggested (https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1381318/am623-how-to-configure-the-main_spi0-of-am623-as-the-host-and-the-fpga-as-the-slave-and-configure-the-main_spi0-of-am623-as-the-dma-mode-and-configure-the-passive-receiving-mode-to-actively-read-the-data-of-the-fpga-buffer-th/5280646#5280646) might be what's needed here; to keep userspace out of the loop managing your interrupt->data transfer chain.

Regards, Andreas