TDA4VM: tda4vm-sdk8.5-I2C-communication failure is a low probability

Hi,

Are you using a custom board?

Does the image show the read data from the camera changing after 50ms?

Thanks,

Neehar

Hi,

Yes,the test is in custom board.

The first column in the picture is the register that reads the I2C3 when the board is powered on and running normally, the second column is the register that reads the I2C3 immediately after the I2C communication is abnormal, and the third column is read again 50ms after the second column is read.

In this case, the I2C communication link is In this case, the I2C communication link is TDAVM-> DS90UB9702-> FPDLINK-> DS90UB935-> ISP GW5200

Thanks,

Qibin

Hi Qibin,

It seems like the register values read are only changing slightly. What registers are these? Is it the same registers everytime?

Also, are there any changes in the configuration in between?

Thanks,

Neehar

Hi Neehar

These registers are retrieved from the TDA4VM data manual, and all three reads use the same function interface, with no operation between the second and third column reads

Thanks,

Qibin

Hi Qibin,

Sorry I did not realize it was the registers from the data manual as I was looking at the addresses for a different device.

Looking deeper into this and the status of the I2C_IRQSTATUS_RAW register, it seems like the AERR or Access Error IRQ status bit is being set. During a read, this register is set to 1 when a read access is performed in the I2C_data register wile the RX FIFO is empty. The corresponding interrupt can be enabled by setting the I2_IRQENABLE_SET[7] AERR_IE bit to 1.

Additionally, can you confirm the bytes of data read in the first two columns?

Thanks,

Neehar

Hi Qibin,

Following up, is this issue still open?
Thanks,

Neehar

Hi Neehar,

The problem still exists. Recently, resources have been limited and there is no time to continue the test

Hi,

I am closing for now, you may reopen later if needed

Thanks,

Neehar