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Hi,
What image are you running?
Best,
Jared
Hi,
I am unable to reproduce the issue with the default image. Do you see the issue with the default image as well, or just with your custom image?
Additionally, can you send the entirety of the dmesg logs?
Best,
Jared
below is the dmesg logs:
root@j721s2-evm:~# dmesg [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080] [ 0.000000] Linux version 5.10.162-imotion (shice@bsp-ThinkCentre-neo-P600IRB-05) (aarch64-none-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 9.2.1 20191025, GNU ld (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 2.33.1.20191209) #1 SMP PREEMPT Fri Jul 26 14:00:54 CST 2024 [ 0.000000] Machine model: Texas Instruments J721S2 EVM [ 0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002880000 (options '') [ 0.000000] printk: bootconsole [ns16550a0] enabled [ 0.000000] efi: UEFI not found. [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader! [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a0000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a0100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a1000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a1100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a2000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 31 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a2100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a4000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 31 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a4100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a6000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a6100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-dma-memory@a7000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-r5f-memory@a7100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 32 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-rtos-ipc-memory-region@a8000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000aa000000, size 96 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-dma-memory@aa000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000b0000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-c71-dma-memory@b0000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000b0100000, size 95 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-c71_0-memory@b0100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000b6000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-c71_1-dma-memory@b6000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000b6100000, size 31 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-c71_1-memory@b6100000, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: initialized node vision_apps_shared-memories, compatible id dma-heap-carveout [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000d8000000, size 64 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-lo@d8000000, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: initialized node zx-app-shared-memories, compatible id dma-heap-carveout [ 0.000000] OF: reserved mem: initialized node zx-ota-shared-memories, compatible id dma-heap-carveout [ 0.000000] OF: reserved mem: initialized node zx-ftc-shared-memories, compatible id dma-heap-carveout [ 0.000000] OF: reserved mem: initialized node zx-ccw-shared-memories, compatible id dma-heap-carveout [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000880000000, size 704 MiB [ 0.000000] OF: reserved mem: initialized node vision-apps-core-heap-memory-hi@880000000, compatible id shared-dma-pool [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000080000000-0x00000000ffffffff] [ 0.000000] DMA32 empty [ 0.000000] Normal [mem 0x0000000100000000-0x00000008ffffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009e7fffff] [ 0.000000] node 0: [mem 0x000000009e800000-0x00000000b7ffffff] [ 0.000000] node 0: [mem 0x00000000b8000000-0x00000000d7ffffff] [ 0.000000] node 0: [mem 0x00000000d8000000-0x00000000dbffffff] [ 0.000000] node 0: [mem 0x00000000dc000000-0x00000000ffffffff] [ 0.000000] node 0: [mem 0x0000000880000000-0x00000008abffffff] [ 0.000000] node 0: [mem 0x00000008ac000000-0x00000008ffffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000008ffffffff] [ 0.000000] On node 0 totalpages: 1048576 [ 0.000000] DMA zone: 8192 pages used for memmap [ 0.000000] DMA zone: 0 pages reserved [ 0.000000] DMA zone: 524288 pages, LIFO batch:63 [ 0.000000] Normal zone: 8192 pages used for memmap [ 0.000000] Normal zone: 524288 pages, LIFO batch:63 [ 0.000000] cma: Failed to reserve 512 MiB [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: Trusted OS migration not required [ 0.000000] psci: SMC Calling Convention v1.2 [ 0.000000] percpu: Embedded 22 pages/cpu s50392 r8192 d31528 u90112 [ 0.000000] pcpu-alloc: s50392 r8192 d31528 u90112 alloc=22*4096 [ 0.000000] pcpu-alloc: [0] 0 [0] 1 [ 0.000000] Detected PIPT I-cache on CPU0 [ 0.000000] CPU features: detected: GIC system register CPU interface [ 0.000000] CPU features: detected: EL2 vector hardening [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI) [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923 [ 0.000000] CPU features: detected: Spectre-BHB [ 0.000000] CPU features: detected: ARM erratum 1742098 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1032192 [ 0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB) [ 0.000000] Memory: 2238880K/4194304K available (9984K kernel code, 1112K rwdata, 3828K rodata, 1664K init, 382K bss, 1955424K reserved, 0K cma-reserved) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 [ 0.000000] rcu: Preemptible hierarchical RCU implementation. [ 0.000000] rcu: RCU event tracing is enabled. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2. [ 0.000000] Trampoline variant of Tasks RCU enabled. [ 0.000000] Tracing variant of Tasks RCU enabled. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode [ 0.000000] GICv3: 960 SPIs implemented [ 0.000000] GICv3: 0 Extended SPIs implemented [ 0.000000] GICv3: Distributor has no Range Selector support [ 0.000000] GICv3: 16 PPIs implemented [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000 [ 0.000000] ITS [mem 0x01820000-0x0182ffff] [ 0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS [ 0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19 [ 0.000000] ITS@0x0000000001820000: allocated 524288 Devices @8ac800000 (flat, esz 8, psz 64K, shr 0) [ 0.000000] ITS: using cache flushing for cmd queue [ 0.000000] GICv3: using LPI property table @0x00000008ac030000 [ 0.000000] GIC: using cache flushing for LPI property table [ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x00000008ac040000 [ 0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns [ 0.000002] sched_clock: 56 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns [ 0.008389] Console: colour dummy device 80x25 [ 0.012959] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000) [ 0.023631] pid_max: default: 32768 minimum: 301 [ 0.028393] LSM: Security Framework initializing [ 0.033156] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) [ 0.040738] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) [ 0.049733] rcu: Hierarchical SRCU implementation. [ 0.054842] Platform MSI: msi-controller@1820000 domain created [ 0.061070] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created [ 0.070382] EFI services will not be available. [ 0.075131] smp: Bringing up secondary CPUs ... [ 0.094160] Detected PIPT I-cache on CPU1 [ 0.094188] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000 [ 0.094201] GICv3: CPU1: using allocated LPI pending table @0x00000008ac050000 [ 0.094245] CPU1: Booted secondary processor 0x0000000001 [0x411fd080] [ 0.094312] smp: Brought up 1 node, 2 CPUs [ 0.123663] SMP: Total of 2 processors activated. [ 0.128469] CPU features: detected: 32-bit EL0 Support [ 0.133724] CPU features: detected: CRC32 instructions [ 0.147316] CPU: All CPU(s) started at EL2 [ 0.151523] alternatives: patching kernel code [ 0.156669] devtmpfs: initialized [ 0.165007] KASLR disabled due to lack of seed [ 0.169686] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 0.179656] futex hash table entries: 512 (order: 3, 32768 bytes, linear) [ 0.186738] pinctrl core: initialized pinctrl subsystem [ 0.192373] DMI not present or invalid. [ 0.196643] NET: Registered protocol family 16 [ 0.201511] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations [ 0.208828] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations [ 0.216838] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations [ 0.225173] thermal_sys: Registered thermal governor 'step_wise' [ 0.225176] thermal_sys: Registered thermal governor 'power_allocator' [ 0.231594] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. [ 0.245237] ASID allocator initialised with 32768 entries [ 0.261234] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages [ 0.268094] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages [ 0.274940] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages [ 0.281787] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages [ 0.289370] cryptd: max_cpu_qlen set to 1000 [ 0.295677] k3-chipinfo 43000014.chipid: Family:J721S2 rev:SR1.0 JTAGID[0x0bb7502f] Detected [ 0.304768] vsys_3v3: supplied by evm_12v0 [ 0.309172] vsys_5v0: supplied by evm_12v0 [ 0.313880] iommu: Default domain type: Translated [ 0.319118] SCSI subsystem initialized [ 0.323151] mc: Linux media interface: v0.10 [ 0.327530] videodev: Linux video capture interface: v2.00 [ 0.333165] pps_core: LinuxPPS API ver. 1 registered [ 0.338237] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 0.347573] PTP clock support registered [ 0.351598] EDAC MC: Ver: 3.0.0 [ 0.355858] clocksource: Switched to clocksource arch_sys_counter [ 0.362225] VFS: Disk quotas dquot_6.6.0 [ 0.366267] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) [ 0.376036] Carveout Heap: Exported 512 MiB at 0x00000000b8000000 [ 0.382325] Carveout Heap: Exported 16 MiB at 0x00000000dc000000 [ 0.388510] Carveout Heap: Exported 48 MiB at 0x00000000dd000000 [ 0.394694] Carveout Heap: Exported 0 MiB at 0x00000000e0000000 [ 0.400791] Carveout Heap: Exported 0 MiB at 0x00000000e0010000 [ 0.406915] NET: Registered protocol family 2 [ 0.411715] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear) [ 0.420425] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear) [ 0.429188] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear) [ 0.437391] TCP bind hash table entries: 32768 (order: 7, 524288 bytes, linear) [ 0.445202] TCP: Hash tables configured (established 32768 bind 32768) [ 0.452067] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear) [ 0.458973] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear) [ 0.466400] NET: Registered protocol family 1 [ 0.470867] NET: Registered protocol family 44 [ 0.475416] PCI: CLS 0 bytes, default 64 [ 0.479840] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available [ 0.490558] Initialise system trusted keyrings [ 0.495232] workingset: timestamp_bits=46 max_order=20 bucket_order=0 [ 0.503487] squashfs: version 4.0 (2009/01/31) Phillip Lougher [ 0.529286] Key type asymmetric registered [ 0.533479] Asymmetric key parser 'x509' registered [ 0.538487] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 244) [ 0.546048] io scheduler mq-deadline registered [ 0.550674] io scheduler kyber registered [ 0.556075] pinctrl-single 4301c000.pinctrl: 101 pins, size 404 [ 0.562274] pinctrl-single 11c000.pinctrl: 72 pins, size 288 [ 0.572312] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled [ 0.584929] brd: module loaded [ 0.592304] loop: module loaded [ 0.597753] tun: Universal TUN/TAP device driver, 1.6 [ 0.603223] igbvf: Intel(R) Gigabit Virtual Function Network Driver [ 0.609631] igbvf: Copyright (c) 2009 - 2012 Intel Corporation. [ 0.615713] sky2: driver version 1.30 [ 0.620003] VFIO - User Level meta-driver version: 0.3 [ 0.625494] i2c /dev entries driver [ 0.629761] sdhci: Secure Digital Host Controller Interface driver [ 0.636091] sdhci: Copyright(c) Pierre Ossman [ 0.640716] sdhci-pltfm: SDHCI platform and OF driver helper [ 0.646973] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping .... [ 0.654047] optee: probing for conduit method. [ 0.658612] optee: revision 3.20 (8e74d476) [ 0.675041] optee: dynamic shared memory is enabled [ 0.684538] optee: initialized driver [ 0.688988] NET: Registered protocol family 17 [ 0.693587] Key type dns_resolver registered [ 0.698042] Loading compiled-in X.509 certificates [ 0.709356] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0008 '8.6.3--1-g2249f (Chill Capybara') [ 0.790377] pca953x 0-0020: supply vcc not found, using dummy regulator [ 0.797228] pca953x 0-0020: using no AI [ 0.824215] omap_i2c 2050000.i2c: bus 0 rev0.12 at 400 kHz [ 0.831499] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 125 domain created [ 0.840137] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 148 domain created [ 0.849538] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 227 domain created [ 0.859009] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 265 created [ 0.870745] ti-udma 311a0000.dma-controller: Number of rings: 48 [ 0.879585] ti-udma 311a0000.dma-controller: Channels: 24 (bchan: 0, tchan: 8, rchan: 16) [ 0.889188] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:272 [ 0.899074] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled [ 0.905833] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64 [ 0.915490] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[878,128] sci-dev-id:259 [ 0.925660] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled [ 0.932419] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64 [ 0.940998] 2820000.serial: ttyS3 at MMIO 0x2820000 (irq = 15, base_baud = 3000000) is a 8250 [ 0.950480] 2850000.serial: ttyS4 at MMIO 0x2850000 (irq = 16, base_baud = 3000000) is a 8250 [ 0.959837] 2880000.serial: ttyS2 at MMIO 0x2880000 (irq = 17, base_baud = 3000000) is a 8250 [ 0.968583] printk: console [ttyS2] enabled [ 0.977020] printk: bootconsole [ns16550a0] disabled [ 0.990336] davinci_mdio c200f00.mdio: Configuring MDIO in manual mode [ 1.035861] davinci_mdio c200f00.mdio: davinci mdio revision 9.7, bus freq 1000000 [ 1.047146] davinci_mdio c200f00.mdio: phy[1]: device c200f00.mdio:01, driver broadcom,bcm89830 [ 1.055919] am65-cpsw-nuss c200000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000 [ 1.068701] am65-cpsw-nuss c200000.ethernet: Use random MAC address [ 1.074960] am65-cpsw-nuss c200000.ethernet: initialized cpsw ale version 1.4 [ 1.082078] am65-cpsw-nuss c200000.ethernet: ALE Table size 64 [ 1.089593] am65-cpsw-nuss c200000.ethernet: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0 [ 1.100857] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010c, freq:200000000, add_val:4 pps:0 [ 1.110061] mmc0: CQHCI version 5.10 [ 1.112190] mmc1: CQHCI version 5.10 [ 1.119323] davinci_gpio 42110000.gpio: IRQ index 0 not found [ 1.125085] davinci_gpio 42110000.gpio: error -ENXIO: IRQ not populated [ 1.141866] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fca100 [ 1.149510] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fca100 [ 1.152424] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit [ 1.157284] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fca100 [ 1.163533] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit [ 1.170539] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fca100 [ 1.190137] ti-udma 285c0000.dma-controller: Channels: 26 (tchan: 13, rchan: 13, gp-rflow: 8) [ 1.200688] ti-udma 31150000.dma-controller: Channels: 60 (tchan: 30, rchan: 30, gp-rflow: 16) [ 1.211541] davinci_mdio c200f00.mdio: Configuring MDIO in manual mode [ 1.255863] davinci_mdio c200f00.mdio: davinci mdio revision 9.7, bus freq 1000000 [ 1.267280] davinci_mdio c200f00.mdio: phy[1]: device c200f00.mdio:01, driver broadcom,bcm89830 [ 1.276080] am65-cpsw-nuss c200000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000 [ 1.288895] am65-cpsw-nuss c200000.ethernet: Use random MAC address [ 1.295172] am65-cpsw-nuss c200000.ethernet: initialized cpsw ale version 1.4 [ 1.302408] am65-cpsw-nuss c200000.ethernet: ALE Table size 64 [ 1.309915] am65-cpsw-nuss c200000.ethernet: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0 [ 1.318928] mmc0: Command Queue Engine enabled [ 1.320633] am65-cpsw-nuss c200000.ethernet: set new flow-id-base 82 [ 1.323393] mmc0: new HS400 MMC card at address 0001 [ 1.336053] mmcblk0: mmc0:0001 CJUD4R 59.6 GiB [ 1.340691] mmcblk0boot0: mmc0:0001 CJUD4R partition 1 31.9 MiB [ 1.346696] mmcblk0boot1: mmc0:0001 CJUD4R partition 2 31.9 MiB [ 1.352730] mmcblk0rpmb: mmc0:0001 CJUD4R partition 3 4.00 MiB, chardev (239:0) [ 1.361967] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 p8 p9 p10 p11 > [ 1.393755] EXT4-fs (mmcblk0p2): recovery complete [ 1.398911] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null) [ 1.407039] VFS: Mounted root (ext4 filesystem) on device 179:2. [ 1.413795] devtmpfs: mounted [ 1.417621] Freeing unused kernel memory: 1664K [ 1.422316] Run /sbin/init as init process [ 1.426420] with arguments: [ 1.426422] /sbin/init [ 1.426424] with environment: [ 1.426426] HOME=/ [ 1.426428] TERM=linux [ 1.469860] systemd[1]: System time before build time, advancing clock. [ 1.479808] mmc1: new high speed SDXC card at address aaaa [ 1.486039] mmcblk1: mmc1:aaaa SD64G 59.5 GiB [ 1.492359] NET: Registered protocol family 10 [ 1.496882] mmcblk1: p1 p2 [ 1.497451] Segment Routing with IPv6 [ 1.512147] systemd[1]: systemd 244.5+ running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR -SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid) [ 1.533960] systemd[1]: Detected architecture arm64. [ 1.572615] systemd[1]: Set hostname to <j721s2-evm>. [ 1.677945] systemd[1]: Configuration file /lib/systemd/system/net_config.service is marked executable. Please remove executable permission bits. Proceeding anyway. [ 1.693270] systemd[1]: /lib/systemd/system/irqbalanced.service:6: Unknown key name 'ConditionCPUs' in section 'Unit', ignoring. [ 1.712908] systemd[1]: Configuration file /lib/systemd/system/S10_idc.service is marked executable. Please remove executable permission bits. Proceeding anyway. [ 1.727767] systemd[1]: Configuration file /lib/systemd/system/S05_ota.service is marked executable. Please remove executable permission bits. Proceeding anyway. [ 1.763345] systemd[1]: Configuration file /lib/systemd/system/usr-ext.mount is marked executable. Please remove executable permission bits. Proceeding anyway. [ 1.779759] systemd[1]: Configuration file /lib/systemd/system/opt-idc.mount is marked executable. Please remove executable permission bits. Proceeding anyway. [ 1.794847] systemd[1]: Configuration file /lib/systemd/system/opt-idc-pdm.mount is marked executable. Please remove executable permission bits. Proceeding anyway. [ 1.810372] systemd[1]: Configuration file /lib/systemd/system/opt-idc-etc-sv3d.mount is marked executable. Please remove executable permission bits. Proceeding anyway. [ 1.826606] systemd[1]: Configuration file /lib/systemd/system/opt-idc-dat.mount is marked executable. Please remove executable permission bits. Proceeding anyway. [ 1.842100] systemd[1]: Configuration file /lib/systemd/system/mnt.mount is marked executable. Please remove executable permission bits. Proceeding anyway. [ 1.860022] random: systemd: uninitialized urandom read (16 bytes read) [ 1.868303] systemd[1]: Created slice system-getty.slice. [ 1.887973] random: systemd: uninitialized urandom read (16 bytes read) [ 1.895244] systemd[1]: Created slice system-serial\x2dgetty.slice. [ 1.915948] random: systemd: uninitialized urandom read (16 bytes read) [ 1.923101] systemd[1]: Created slice User and Session Slice. [ 1.944109] systemd[1]: Started Dispatch Password Requests to Console Directory Watch. [ 1.968015] systemd[1]: Started Forward Password Requests to Wall Directory Watch. [ 1.992049] systemd[1]: Reached target Paths. [ 2.007936] systemd[1]: Reached target Remote File Systems. [ 2.027914] systemd[1]: Reached target Slices. [ 2.043923] systemd[1]: Reached target Swap. [ 2.062021] systemd[1]: Listening on Process Core Dump Socket. [ 2.084114] systemd[1]: Listening on initctl Compatibility Named Pipe. [ 2.109919] systemd[1]: Condition check resulted in Journal Audit Socket being skipped. [ 2.118392] systemd[1]: Listening on Journal Socket (/dev/log). [ 2.140267] systemd[1]: Listening on Journal Socket. [ 2.156324] systemd[1]: Listening on Network Service Netlink Socket. [ 2.180181] systemd[1]: Listening on udev Control Socket. [ 2.200079] systemd[1]: Listening on udev Kernel Socket. [ 2.222689] systemd[1]: Mounting Huge Pages File System... [ 2.242836] systemd[1]: Mounting Temporary Directory (/tmp)... [ 2.260128] systemd[1]: Condition check resulted in File System Check on Root Device being skipped. [ 2.272816] systemd[1]: Starting Journal Service... [ 2.280197] systemd-journald[154]: Configuration file /etc/systemd/journald.conf is marked executable. Please remove executable permission bits. Proceeding anyway. [ 2.300478] systemd[1]: Starting Load Kernel Modules... [ 2.318607] systemd[1]: Starting Remount Root and Kernel File Systems... [ 2.335330] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this. [ 2.351534] systemd[1]: Starting Create Static Device Nodes in /dev... [ 2.353931] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null) [ 2.382895] systemd[1]: Starting udev Coldplug all Devices... [ 2.392005] sja1105 spi0.1: Probed switch chip: SJA1105S [ 2.410357] sja1105 spi0.1: Enabled switch tagging [ 2.411377] systemd[1]: Started Journal Service. [ 2.415437] sja1105 spi0.1: configuring for fixed/rgmii-txid link mode [ 2.427552] sja1105 spi0.1: Link is Up - 1Gbps/Full - flow control off [ 2.436559] sja1105 spi0.1 swp1 (uninitialized): PHY [c200f00.mdio:01] driver [broadcom,bcm89830] (irq=POLL) [ 2.450597] sja1105 spi0.1 swp1: configuring for phy/rmii link mode [ 2.459711] sja1105 spi0.1 swp1: Link is Up - 100Mbps/Full - flow control off [ 2.470667] sja1105 spi0.1: configuring for fixed/rgmii-txid link mode [ 2.478391] sja1105 spi0.1: configuring for fixed/rgmii-id link mode [ 2.478604] sja1105 spi0.1: Link is Up - 1Gbps/Full - flow control off [ 2.485706] sja1105 spi0.1: configuring for fixed/sgmii link mode [ 2.492583] sja1105 spi0.1: Link is Up - 1Gbps/Full - flow control off [ 2.497765] device eth0 entered promiscuous mode [ 2.504526] sja1105 spi0.1: Link is Up - 1Gbps/Full - flow control off [ 2.508598] DSA: tree 0 setup [ 2.628870] systemd-journald[154]: Received client request to flush runtime journal. [ 2.925224] random: systemd: uninitialized urandom read (16 bytes read) [ 2.936829] random: systemd: uninitialized urandom read (16 bytes read) [ 2.960010] random: systemd-journal: uninitialized urandom read (16 bytes read) [ 3.000429] random: crng init done [ 3.003841] random: 41 urandom warning(s) missed due to ratelimiting [ 3.016263] CAN device driver interface [ 3.067994] k3-dsp-rproc 64800000.dsp: assigned reserved memory node vision-apps-c71-dma-memory@b0000000 [ 3.119709] vdec 4210000.video-codec: Direct firmware load for wave521c_codec_fw.bin failed with error -2 [ 3.288980] platform 5c00000.r5f: configured R5F for remoteproc mode [ 3.300325] vdec 4210000.video-codec: request_firmware, fail: -2 [ 3.314130] k3-dsp-rproc 64800000.dsp: configured DSP for remoteproc mode [ 3.323070] vdec 4210000.video-codec: wave5_vpu_load_firmware, fail: -2 [ 3.331222] platform 5c00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a2000000 [ 3.343369] remoteproc remoteproc0: 64800000.dsp is available [ 3.365930] k3-dsp-rproc 65800000.dsp: assigned reserved memory node vision-apps-c71_1-dma-memory@b6000000 [ 3.380810] k3-dsp-rproc 65800000.dsp: configured DSP for remoteproc mode [ 3.391082] vdec: probe of 4210000.video-codec failed with error -2 [ 3.399115] remoteproc remoteproc1: 5c00000.r5f is available [ 3.417103] remoteproc remoteproc2: 65800000.dsp is available [ 3.454775] remoteproc remoteproc0: powering up 64800000.dsp [ 3.461607] remoteproc remoteproc0: Booting fw image j721s2-c71_0-fw, size 23625080 [ 3.474043] remoteproc remoteproc0: unsupported resource 65538 [ 3.486814] remoteproc remoteproc1: powering up 5c00000.r5f [ 3.497651] k3-dsp-rproc 64800000.dsp: booting DSP core using boot addr = 0xb0200000 [ 3.505466] remoteproc remoteproc1: Booting fw image j721s2-main-r5f0_0-fw, size 5517460 [ 3.531647] remoteproc0#vdev0buffer: assigned reserved memory node vision-apps-c71-dma-memory@b0000000 [ 3.543257] remoteproc1#vdev0buffer: assigned reserved memory node vision-apps-r5f-dma-memory@a2000000 [ 3.553615] EXT4-fs (mmcblk0p11): recovery complete [ 3.558103] virtio_rpmsg_bus virtio0: rpmsg host is online [ 3.569900] EXT4-fs (mmcblk0p11): mounted filesystem with ordered data mode. Opts: (null) [ 3.583383] virtio_rpmsg_bus virtio1: rpmsg host is online [ 3.597487] remoteproc remoteproc2: powering up 65800000.dsp [ 3.610692] remoteproc remoteproc2: Booting fw image j721s2-c71_1-fw, size 12206696 [ 3.622448] remoteproc1#vdev0buffer: registered virtio1 (type 7) [ 3.633482] pps-gpio pps: failed to request PPS GPIO [ 3.639325] remoteproc0#vdev0buffer: registered virtio0 (type 7) [ 3.649085] remoteproc remoteproc1: remote processor 5c00000.r5f is now up [ 3.664362] remoteproc remoteproc0: remote processor 64800000.dsp is now up [ 3.673943] remoteproc remoteproc2: unsupported resource 65538 [ 3.711418] k3-dsp-rproc 65800000.dsp: booting DSP core using boot addr = 0xb6200000 [ 3.719264] pps-gpio: probe of pps failed with error -22 [ 3.725759] EXT4-fs (mmcblk0p6): recovery complete [ 3.736014] virtio_rpmsg_bus virtio0: creating channel rpmsg_chrdev addr 0xd [ 3.744297] virtio_rpmsg_bus virtio1: creating channel rpmsg_chrdev addr 0xd [ 3.756621] remoteproc2#vdev0buffer: assigned reserved memory node vision-apps-c71_1-dma-memory@b6000000 [ 3.770023] EXT4-fs (mmcblk0p6): mounted filesystem with ordered data mode. Opts: (null) [ 3.780577] virtio_rpmsg_bus virtio2: rpmsg host is online [ 3.791089] ext4 filesystem being mounted at /usr/ext supports timestamps until 2038 (0x7fffffff) [ 3.800163] remoteproc2#vdev0buffer: registered virtio2 (type 7) [ 3.809701] remoteproc remoteproc2: remote processor 65800000.dsp is now up [ 3.811383] virtio_rpmsg_bus virtio2: creating channel rpmsg_chrdev addr 0xd [ 3.832249] virtio_rpmsg_bus virtio2: creating channel rpmsg_chrdev addr 0x15 [ 3.848038] virtio_rpmsg_bus virtio2: creating channel ti.ipc4.ping-pong addr 0xe [ 3.864042] virtio_rpmsg_bus virtio0: creating channel rpmsg_chrdev addr 0x15 [ 3.879359] virtio_rpmsg_bus virtio0: creating channel ti.ipc4.ping-pong addr 0xe [ 3.894126] virtio_rpmsg_bus virtio1: creating channel rpmsg_chrdev addr 0x15 [ 3.931653] virtio_rpmsg_bus virtio1: creating channel ti.ipc4.ping-pong addr 0xe [ 3.984901] EXT4-fs (mmcblk0p8): recovery complete [ 3.992002] EXT4-fs (mmcblk0p8): mounted filesystem with ordered data mode. Opts: (null) [ 4.010788] ext4 filesystem being mounted at /opt/idc supports timestamps until 2038 (0x7fffffff) [ 4.085796] EXT4-fs (mmcblk0p10): recovery complete [ 4.096483] EXT4-fs (mmcblk0p10): mounted filesystem with ordered data mode. Opts: (null) [ 4.125380] EXT4-fs (mmcblk0p9): recovery complete [ 4.130508] EXT4-fs (mmcblk0p9): mounted filesystem with ordered data mode. Opts: (null) [ 4.145027] ext4 filesystem being mounted at /opt/idc/etc/sv3d supports timestamps until 2038 (0x7fffffff) [ 4.199989] EXT4-fs (mmcblk0p3): recovery complete [ 4.206361] EXT4-fs (mmcblk0p3): mounted filesystem with ordered data mode. Opts: (null) [ 4.223405] ext4 filesystem being mounted at /opt/idc/pdm supports timestamps until 2038 (0x7fffffff) [ 5.024130] am65-cpsw-nuss c200000.ethernet eth0: configuring for fixed/rgmii-rxid link mode [ 5.032677] am65-cpsw-nuss c200000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off [ 5.201092] 8021q: 802.1Q VLAN Support v1.8 [ 5.210312] 8021q: adding VLAN 0 to HW filter on device eth0 [ 11.240442] hrtimer: interrupt took 101070 ns
Hi,
Is this a custom image for a custom board? If so, can you send all the entire device tree source files?
Best,
Jared
Hi Jared,
Yes, this is a custom image for a custom board. below is device tree.
a. k3-j721s2-common-proc-board-uarts.dts
// SPDX-License-Identifier: GPL-2.0
/*
* DT Overlay File for extending mcu uart 0 and wkup uart 0 support to kernel
* for J721S2 SOC
*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/pinctrl/k3.h>
/ {
fragment@4 {
target-path = "/";
__overlay__ {
aliases {
serial0 = "/bus@100000/bus@28380000/serial@42300000";
serial1 = "/bus@100000/bus@28380000/serial@40a00000";
};
};
};
};
&wkup_pmx0{
mcu_uart0_pins_default: mcu-uart0-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
J721S2_WKUP_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
};
};
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
};
&wkup_pmx0 {
wkup_uart0_pins_default: wkup-uart0-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>;
};
};
&wkup_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
b. k3-j721s2-common-proc-board.dts
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*
* Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM
*/
/dts-v1/;
#include "k3-j721s2-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
#include "k3-j721s2-rtos-memory-map.dtsi"
/ {
compatible = "ti,j721s2-evm", "ti,j721s2";
model = "Texas Instruments J721S2 EVM";
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x2880000 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait";
};
aliases {
serial2 = &main_uart8;
serial3 = &main_uart2;
serial4 = &main_uart5;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
can0 = &main_mcan16;
can1 = &mcu_mcan0;
can2 = &mcu_mcan1;
can3 = &main_mcan3;
can4 = &main_mcan5;
ethernet1 = &main_cpsw_port1;
};
evm_12v0: fixedregulator-evm12v0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 {
/* Output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: fixedregulator-vsys5v0 {
/* Output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: fixedregulator-sd {
/* Output of TPS22918 */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
vdd_sd_dv: gpio-regulator-TLV71033 {
/* Output of TLV71033 */
compatible = "regulator-gpio";
regulator-name = "tlv71033";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_pins_default>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vsys_5v0>;
gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0>,
<3300000 0x1>;
status = "disabled";
};
transceiver1: can-phy1 {
compatible = "ti,tcan1043";
#phy-cells = <0>;
max-bitrate = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>;
enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
};
transceiver2: can-phy2 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
};
transceiver3: can-phy3 {
compatible = "ti,tcan1043";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
mux-states = <&mux0 1>;
};
transceiver4: can-phy4 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>;
mux-states = <&mux1 1>;
};
dp0_pwr_3v3: fixedregulator-dp0-prw {
compatible = "regulator-fixed";
regulator-name = "dp0-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&exp4 0 0>; /* P0 - DP0_PWR_SW_EN */
enable-active-high;
};
dp1_pwr_3v3: regulator-dp1-prw {
compatible = "regulator-fixed";
regulator-name = "dp1-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */
enable-active-high;
regulator-always-on;
};
dp0: dp0-connector {
compatible = "dp-connector";
label = "DP0";
type = "full-size";
dp-pwr-supply = <&dp0_pwr_3v3>;
status = "disabled";
port {
dp0_connector_in: endpoint {
remote-endpoint = <&dp0_out>;
};
};
};
panel {
compatible = "ti,panel-edp";
power-supply = <&dp1_pwr_3v3>;
status = "disabled";
port {
dp1_panel_in: endpoint {
remote-endpoint = <&dp1_out>;
};
};
};
/*
pps:pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pps_pins_default>;
gpios = <&main_gpio0 24 GPIO_ACTIVE_HIGH>;
assert-falling-edge; //a72 core pps falling edg
status = "okay";
};
*/
pps:pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&wkup_pps_pins_default>;
gpios = <&wkup_gpio0 15 GPIO_ACTIVE_HIGH>;
assert-falling-edge; //a72 core pps falling edg
status = "okay";
};
};
&main_i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c4_pins_default>;
clock-frequency = <400000>;
status = "disabled";
exp4: gpio@20 {
compatible = "ti,tca6408";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&main_pmx0 {
main_uart8_pins_default: main-uart8-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
J721S2_IOPAD(0x038, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
J721S2_IOPAD(0x03C, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>;
};
main_uart2_pins_default: main-uart2-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x064, PIN_INPUT, 11) /* (W28) MCAN0_TX.UART2_RXD */
J721S2_IOPAD(0x068, PIN_OUTPUT, 11) /* (U28) MCAN0_RX.UART2_TXD */
>;
};
main_uart5_pins_default: main-uart5-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x008, PIN_INPUT, 11) /* (AC24) MCAN12_RX.UART5_RXD */
J721S2_IOPAD(0x004, PIN_OUTPUT, 11) /* (W25) MCAN12_TX.UART5_TXD */
>;
};
main_i2c3_pins_default: main-i2c3-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>;
};
main_usbss0_pins_default: main-usbss0-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
};
main_mcan3_pins_default: main-mcan3-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */
J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */
>;
};
main_mcan5_pins_default: main-mcan5-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */
J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */
>;
};
main_i2c4_pins_default: main-i2c4-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) I2C4_SCL */
J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) I2C4_SDA */
>;
};
dp0_pins_default: dp0-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x0b8, PIN_INPUT, 3) /* (AA24) MCASP1_ACLKX.DP0_HPD */
>;
};
main_i2c5_pins_default: main-i2c5-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */
J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */
>;
};
main_spi6_pins_default: main-spi6-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x030, PIN_OUTPUT, 8) /* (T26) SPI6 CLOCK*/
J721S2_IOPAD(0x078, PIN_OUTPUT, 8) /* (Y25) CS1*/
J721S2_IOPAD(0x0C4, PIN_OUTPUT, 8) /* (AB26) D0*/
J721S2_IOPAD(0x074, PIN_INPUT, 8) /* (R28) D1*/
>;
};
main_cpsw_mdio_pins_default: main-cpsw-mdio-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
>;
};
rgmii1_pins_default: rgmii1-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */
J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */
J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */
J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */
>;
};
pps_pins_default: pps-pins-default{
pinctrl-single,pins = <
J721S2_IOPAD(0x060, PIN_INPUT, 7) /* (AC27) GPIO0_24,for pps */
>;
};
};
&wkup_pmx0 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
>;
};
mcu_mdio_pins_default: mcu-mdio-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
>;
};
mcu_mcan0_pins_default: mcu-mcan0-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
>;
};
mcu_mcan1_pins_default: mcu-mcan1-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
>;
};
mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */
J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */
>;
};
mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
>;
};
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
>;
};
wkup_pps_pins_default: wkup-pps-pins-default{
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 7) /* (AC27) GPIO0_24,for pps */
>;
};
};
&main_gpio0 {
status = "okay";
};
&main_gpio4 {
status = "disabled";
};
&main_gpio6 {
status = "disabled";
};
&wkup_gpio0 {
status = "okay";
};
&wkup_gpio1 {
status = "disabled";
};
&wkup_uart0 {
status = "disabled";
};
&mcu_uart0 {
status = "disabled";
};
&main_uart0 {
status = "disabled";
};
&main_uart1 {
status = "disabled";
};
&main_uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart2_pins_default>;
power-domains = <&k3_pds 351 TI_SCI_PD_SHARED>;
reset-gpios = <&exp5 5 GPIO_ACTIVE_HIGH>;
};
&main_uart3 {
status = "disabled";
};
&main_uart4 {
status = "disabled";
};
&main_uart5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart5_pins_default>;
power-domains = <&k3_pds 354 TI_SCI_PD_SHARED>;
};
&main_uart6 {
status = "disabled";
};
&main_uart7 {
status = "disabled";
};
&main_uart8 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
};
&main_uart9 {
status = "disabled";
};
&main_i2c0 {
clock-frequency = <400000>;
status = "disabled";
exp1: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ",
"PCIE_2L_EP_RST_EN", "PCIE_1L_MODE_SEL", "PCIE_1L_PERSTZ",
"PCIE_1L_RC_RSTZ", "PCIE_1L_EP_RST_EN", "PCIE_2L_PRSNT#",
"PCIE_1L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", "EXP_MUX1",
"EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTz";
};
exp2: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN",
"USBC_MODE_SEL1", "USBC_MODE_SEL0", "MCAN0_EN", "MCAN0_STB#",
"MUX_SPAREMUX_SPARE", "MCASP/TRACE_MUX_S0", "MCASP/TRACE_MUX_S1",
"MLB_MUX_SEL", "MCAN_MUX_SEL", "MCASP2/SPI3_MUX_SEL", "PCIe_CLKREQn_MUX_SEL",
"CDCI2_RSTZ", "ENET_EXP_PWRDN", "ENET_EXP_RESETZ", "ENET_I2CMUX_SEL",
"ENET_EXP_SPARE2", "M2PCIE_RTSZ", "USER_INPUT1", "USER_LED1", "USER_LED2";
};
};
&main_i2c1 {
status = "disabled";
};
&main_i2c2 {
status = "disabled";
};
&main_i2c3 {
status = "disabled";
};
&main_i2c4 {
status = "disabled";
};
&main_i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c5_pins_default>;
clock-frequency = <400000>;
status = "okay";
exp5: gpio@20 {
compatible = "ti,tca6408";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&main_i2c6 {
status = "disabled";
};
&main_spi0 {
status = "disabled";
};
&main_spi1 {
status = "disabled";
};
&main_spi2 {
status = "disabled";
};
&main_spi3 {
status = "disabled";
};
&main_spi4 {
status = "disabled";
};
&main_spi5 {
status = "disabled";
};
&main_spi7 {
status = "disabled";
};
&main_spi6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi6_pins_default>;
ti,pindir-d0-out-d1-in;
ti,spi-num-cs = <2>;
sja1105: ethernet-switch@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,sja1105s";
/* 12 MHz */
spi-max-frequency = <12000000>;
/* Sample data on trailing clock edge */
spi-cpha;
/* SPI controller settings for SJA1105 timing requirements */
fsl,spi-cs-sck-delay = <1000>;
fsl,spi-sck-cs-delay = <1000>;
reset-gpios = <&exp5 4 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
label = "cpu";
ethernet = <&main_cpsw>;
phy-mode = "rgmii-txid";
reg = <0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
label = "swp1";
phy-mode = "rmii";
local-mac-address = [ 00 0a 35 00 00 00 ];
phy-handle = <&main_cpsw_phy0>;
reg = <1>;
};
port@2 {
label = "mcu";
phy-mode = "rgmii-txid";
reg = <2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@3 {
label = "j3";
phy-mode = "rgmii-id";
reg = <3>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@4 {
label = "test";
phy-mode = "sgmii";
reg = <4>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
&mcu_spi0 {
status = "disabled";
};
&mcu_spi1 {
status = "disabled";
};
&mcu_spi2 {
status = "disabled";
};
&main_sdhci0 {
/* eMMC */
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&main_sdhci1 {
/* SD card */
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
disable-wp;
vmmc-supply = <&vsys_3v3>;
vqmmc-supply = <&vsys_3v3>;
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
status = "disabled";
};
&davinci_mdio {
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&serdes_ln_ctrl {
status = "disabled";
idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
<J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
};
&serdes_refclk {
clock-frequency = <100000000>;
status = "disabled";
};
&serdes0 {
status = "disabled";
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
};
&usb_serdes_mux {
idle-states = <1>; /* USB0 to SERDES lane 1 */
status = "disabled";
};
&edp_serdes_mux {
idle-states = <1>; /* EDP0 to SERDES lane 2/3 */
status = "disabled";
};
&usbss0 {
pinctrl-0 = <&main_usbss0_pins_default>;
pinctrl-names = "default";
ti,vbus-divider;
ti,usb2-only;
status = "disabled";
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
status = "disabled";
};
&pcie1_rc {
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
status = "disabled";
};
&pcie1_ep {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
status = "disabled";
};
&ospi1 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
status = "disabled";
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&tscadc0 {
status = "disabled";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&tscadc1 {
status = "disabled";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&mcu_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>;
phys = <&transceiver1>;
status = "disabled";
};
&mcu_mcan1 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan1_pins_default>;
phys = <&transceiver2>;
status = "disabled";
};
&dss {
status = "disabled";
/*
* These clock assignments are chosen to enable the following outputs:
*
* VP0 - DisplayPort SST
* VP1 - DPI0
* VP2 - DSI
* VP3 - DPI1
*/
assigned-clocks = <&k3_clks 158 2>,
<&k3_clks 158 5>,
<&k3_clks 158 14>,
<&k3_clks 158 18>;
assigned-clock-parents = <&k3_clks 158 3>,
<&k3_clks 158 7>,
<&k3_clks 158 16>,
<&k3_clks 158 22>;
};
&dss_ports {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpi0_out: endpoint {
remote-endpoint = <&dp0_in>;
};
};
port@2 {
reg = <2>;
dpi2_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
&dsi0_ports {
status = "disabled";
port@0 {
reg = <0>;
dsi0_out: endpoint {
remote-endpoint = <&dp1_in>;
};
};
port@1 {
reg = <1>;
dsi0_in: endpoint {
remote-endpoint = <&dpi2_out>;
};
};
};
&dsi_edp_bridge_ports {
status = "disabled";
port@0 {
reg = <0>;
dp1_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
dp1_out: endpoint {
remote-endpoint = <&dp1_panel_in>;
};
};
};
&mhdp {
pinctrl-names = "default";
pinctrl-0 = <&dp0_pins_default>;
cdns,no-hpd;
status = "disabled";
};
&dp0_ports {
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
reg = <0>;
dp0_in: endpoint {
remote-endpoint = <&dpi0_out>;
};
};
port@4 {
reg = <4>;
dp0_out: endpoint {
remote-endpoint = <&dp0_connector_in>;
};
};
};
&main_mcan0 {
status = "disabled";
};
&main_mcan1 {
status = "disabled";
};
&main_mcan2 {
status = "disabled";
};
&main_mcan3 {
pinctrl-names = "default";
pinctrl-0 = <&main_mcan3_pins_default>;
phys = <&transceiver3>;
status = "disabled";
};
&main_mcan4 {
status = "disabled";
};
&main_mcan5 {
pinctrl-names = "default";
pinctrl-0 = <&main_mcan5_pins_default>;
phys = <&transceiver4>;
status = "disabled";
};
&main_mcan6 {
status = "disabled";
};
&main_mcan7 {
status = "disabled";
};
&main_mcan8 {
status = "disabled";
};
&main_mcan9 {
status = "disabled";
};
&main_mcan10 {
status = "disabled";
};
&main_mcan11 {
status = "disabled";
};
&main_mcan12 {
status = "disabled";
};
&main_mcan13 {
status = "disabled";
};
&main_mcan14 {
status = "disabled";
};
&main_mcan15 {
status = "disabled";
};
&main_mcan17 {
status = "disabled";
};
&main_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&main_cpsw_mdio_pins_default
&rgmii1_pins_default>;
status = "okay";
};
&main_cpsw_mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&exp5 7 GPIO_ACTIVE_LOW>;
main_cpsw_phy0: ethernet-phy@1 {
compatible = "broadcom,bcm89830", "ethernet-phy-ieee802.3-c45";
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&main_cpsw_port1 {
phy-mode = "rgmii-rxid";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&csi0_port0 {
status = "disabled";
};
&csi0_port1 {
status = "disabled";
};
&csi0_port2 {
status = "disabled";
};
&csi0_port3 {
status = "disabled";
};
&csi0_port4 {
status = "disabled";
};
&csi1_port0 {
status = "disabled";
};
&csi1_port1 {
status = "disabled";
};
&csi1_port2 {
status = "disabled";
};
&csi1_port3 {
status = "disabled";
};
&csi1_port4 {
status = "disabled";
};
&wkup_i2c0 {
status = "disabled";
tps6594x: tps6594x@48 {
compatible = "ti,tps6594x";
reg = <0x48>;
ti,system-power-controller;
rtc {
compatible = "ti,tps6594x-rtc";
};
gpio {
compatible = "ti,tps6594x-gpio";
};
};
};
&serdes_wiz0 {
status = "disabled";
};
&dss {
status = "disabled";
};
&dphy0 {
status = "disabled";
};
&ti_csi2rx0 {
status = "disabled";
};
&ti_csi2rx1 {
status = "disabled";
};
&ti_csi2rx1 {
status = "disabled";
};
&dphy_rx0 {
status = "disabled";
};
&dphy_rx1 {
status = "disabled";
};
&mcu_i2c0 {
status = "disabled";
};
&mcu_i2c1 {
status = "disabled";
};
&fss {
status = "disabled";
};
&wkup_vtm0 {
status = "disabled";
};
c. k3-j721s2-main.dtsi
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721S2 SoC Family Main Domain peripherals
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy.h>
/ {
serdes_refclk: serdes-refclk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
};
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x0 0x70000000 0x0 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x70000000 0x400000>;
atf-sram@0 {
reg = <0x0 0x20000>;
};
vpu_sram: vpu-sram@20000 {
reg = <0x20000 0x1f800>;
};
tifs-sram@1f0000 {
reg = <0x1f0000 0x10000>;
};
l3cache-sram@200000 {
reg = <0x200000 0x200000>;
};
};
scm_conf: scm-conf@104000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00 0x00104000 0x00 0x18000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00104000 0x18000>;
serdes_ln_ctrl: mux-controller0 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
<0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
};
usb_serdes_mux: mux-controller1 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
edp_serdes_mux: mux-controller2 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
/* EDP0 to SERDES0 lane 0/1 or 2/3 mux */
mux-reg-masks = <0x310 0x10000000>;
};
phy_gmii_sel_cpsw: phy@34 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x34 0x4>;
#phy-cells = <1>;
};
ehrpwm_tbclk: clock-controller@140 {
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
reg = <0x140 0x18>;
#clock-cells = <1>;
};
};
main_ehrpwm0: pwm@3000000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3000000 0x00 0x100>;
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
clock-names = "tbclk", "fck";
};
main_ehrpwm1: pwm@3010000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3010000 0x00 0x100>;
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
clock-names = "tbclk", "fck";
};
main_ehrpwm2: pwm@3020000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3020000 0x00 0x100>;
power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
clock-names = "tbclk", "fck";
};
main_ehrpwm3: pwm@3030000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3030000 0x00 0x100>;
power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
clock-names = "tbclk", "fck";
};
main_ehrpwm4: pwm@3040000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3040000 0x00 0x100>;
power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
clock-names = "tbclk", "fck";
};
main_ehrpwm5: pwm@3050000 {
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x00 0x3050000 0x00 0x100>;
power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
clock-names = "tbclk", "fck";
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
<0x00 0x01900000 0x00 0x100000>; /* GICR */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <148>;
ti,interrupt-ranges = <8 392 56>;
};
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x0 0x11c000 0x0 0x120>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_crypto: crypto@4e00000 {
compatible = "ti,j721e-sa2ul";
reg = <0x00 0x4e00000 0x00 0x1200>;
power-domains = <&k3_pds 297 TI_SCI_PD_SHARED>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
<&main_udmap 0x4a41>;
dma-names = "tx", "rx1", "rx2";
};
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 146 3>;
clock-names = "fclk";
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
};
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x200>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 350 3>;
clock-names = "fclk";
power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
};
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x200>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 351 3>;
clock-names = "fclk";
power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
};
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x200>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 352 3>;
clock-names = "fclk";
power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
};
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x200>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 353 3>;
clock-names = "fclk";
power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
};
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x200>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 354 3>;
clock-names = "fclk";
power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
};
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x200>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 355 3>;
clock-names = "fclk";
power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
};
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x200>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 356 3>;
clock-names = "fclk";
power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
};
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x200>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 357 3>;
clock-names = "fclk";
power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
};
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x200>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 358 3>;
clock-names = "fclk";
power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
};
gpu: gpu@4e20000000 {
compatible = "ti,j721s2-pvr", "img,pvr-bxs64";
reg = <0x4e 0x20000000 0x00 0x80000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 373 TI_SCI_PD_EXCLUSIVE>;
power-domain-names = "gpu_0", "gpucore_0";
clocks = <&k3_clks 130 1>;
};
main_gpio0: gpio@600000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00600000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <145>, <146>, <147>, <148>, <149>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 111 0>;
clock-names = "gpio";
};
main_gpio2: gpio@610000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00610000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <154>, <155>, <156>, <157>, <158>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 112 0>;
clock-names = "gpio";
};
main_gpio4: gpio@620000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00620000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <163>, <164>, <165>, <166>, <167>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
};
main_gpio6: gpio@630000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00630000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <172>, <173>, <174>, <175>, <176>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "gpio";
};
main_i2c0: i2c@2000000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02000000 0x00 0x100>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 214 1>;
clock-names = "fck";
power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c1: i2c@2010000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02010000 0x00 0x100>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 215 1>;
clock-names = "fck";
power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c2: i2c@2020000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02020000 0x00 0x100>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 216 1>;
clock-names = "fck";
power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c3: i2c@2030000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02030000 0x00 0x100>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 217 1>;
clock-names = "fck";
power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c4: i2c@2040000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02040000 0x00 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 218 1>;
clock-names = "fck";
power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c5: i2c@2050000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02050000 0x00 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 219 1>;
clock-names = "fck";
power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c6: i2c@2060000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02060000 0x00 0x100>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 220 1>;
clock-names = "fck";
power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
};
vpu: video-codec@4210000 {
compatible = "cnm,cm521c-vpu";
reg = <0x00 0x4210000 0x00 0x10000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 179 2>;
clock-names = "vcodec";
power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
sram = <&vpu_sram>;
};
main_sdhci0: mmc@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x00 0x04f80000 0x00 0x1000>,
<0x00 0x04f88000 0x00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 98 1>;
assigned-clock-parents = <&k3_clks 98 2>;
bus-width = <8>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x6>;
ti,otap-del-sel-hs200 = <0x8>;
ti,otap-del-sel-hs400 = <0x5>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,strobe-sel = <0x77>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
dma-coherent;
};
main_sdhci1: mmc@4fb0000 {
compatible = "ti,j721e-sdhci-4bit";
reg = <0x00 0x04fb0000 0x00 0x1000>,
<0x00 0x04fb8000 0x00 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 99 1>;
assigned-clock-parents = <&k3_clks 99 2>;
bus-width = <4>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
/* Masking support for SDR104 capability */
sdhci-caps-mask = <0x8000000F 0x00000000>;
};
main_navss: bus@30000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci-dev-id = <224>;
dma-coherent;
dma-ranges;
main_navss_intr: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
reg = <0x00 0x310e0000 0x00 0x4000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <227>;
ti,interrupt-ranges = <0 64 64>,
<64 448 64>,
<128 672 64>;
};
main_udmass_inta: msi-controller@33d00000 {
compatible = "ti,sci-inta";
reg = <0x00 0x33d00000 0x00 0x100000>;
interrupt-controller;
#interrupt-cells = <0>;
interrupt-parent = <&main_navss_intr>;
msi-controller;
ti,sci = <&sms>;
ti,sci-dev-id = <265>;
ti,interrupt-ranges = <0 0 256>;
ti,unmapped-event-sources = <&main_bcdma_csi>;
};
secure_proxy_main: mailbox@32c00000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x32c00000 0x00 0x100000>,
<0x00 0x32400000 0x00 0x100000>,
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
hwspinlock: spinlock@30e00000 {
compatible = "ti,am654-hwspinlock";
reg = <0x00 0x30e00000 0x00 0x1000>;
#hwlock-cells = <1>;
};
mailbox0_cluster0: mailbox@31f80000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f80000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster1: mailbox@31f81000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f81000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster2: mailbox@31f82000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f82000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster3: mailbox@31f83000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f83000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster4: mailbox@31f84000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f84000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster5: mailbox@31f85000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f85000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster6: mailbox@31f86000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f86000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster7: mailbox@31f87000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f87000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster8: mailbox@31f88000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f88000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster9: mailbox@31f89000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f89000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster10: mailbox@31f8a000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f8a000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox0_cluster11: mailbox@31f8b000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f8b000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster0: mailbox@31f90000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f90000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster1: mailbox@31f91000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f91000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster2: mailbox@31f92000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f92000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster3: mailbox@31f93000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f93000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster4: mailbox@31f94000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f94000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster5: mailbox@31f95000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f95000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster6: mailbox@31f96000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f96000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster7: mailbox@31f97000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f97000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster8: mailbox@31f98000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f98000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster9: mailbox@31f99000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f99000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster10: mailbox@31f9a000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f9a000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
mailbox1_cluster11: mailbox@31f9b000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f9b000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
};
main_ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
ti,sci-dev-id = <259>;
msi-parent = <&main_udmass_inta>;
};
main_udmap: dma-controller@31150000 {
compatible = "ti,j721e-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x80000>,
<0x0 0x35000000 0x0 0x200000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <263>;
ti,ringacc = <&main_ringacc>;
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
<0x0f>, /* TX_HCHAN */
<0x10>; /* TX_UHCHAN */
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>, /* RX_HCHAN */
<0x0c>; /* RX_UHCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
main_bcdma_csi: dma-controller@311a0000 {
compatible = "ti,j721s2-dmss-bcdma-csi";
reg = <0x00 0x311a0000 0x00 0x100>,
<0x00 0x35d00000 0x00 0x20000>,
<0x00 0x35c00000 0x00 0x10000>,
<0x00 0x35e00000 0x00 0x80000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <3>;
ti,sci = <&sms>;
ti,sci-dev-id = <225>;
ti,sci-rm-range-rchan = <0x21>;
ti,sci-rm-range-tchan = <0x22>;
};
cpts@310d0000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x310d0000 0x0 0x400>;
reg-names = "cpts";
clocks = <&k3_clks 226 5>;
clock-names = "cpts";
interrupts-extended = <&main_navss_intr 391>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
ti,cpts-ext-ts-inputs = <8>;
};
};
main_cpsw: ethernet@c200000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0xc200000 0x0 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
dma-coherent;
clocks = <&k3_clks 28 28>;
clock-names = "fck";
power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
dmas = <&main_udmap 0xc640>,
<&main_udmap 0xc641>,
<&main_udmap 0xc642>,
<&main_udmap 0xc643>,
<&main_udmap 0xc644>,
<&main_udmap 0xc645>,
<&main_udmap 0xc646>,
<&main_udmap 0xc647>,
<&main_udmap 0x4640>;
dma-names = "tx0", "tx1", "tx2", "tx3",
"tx4", "tx5", "tx6", "tx7",
"rx";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
main_cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
label = "port1";
phys = <&phy_gmii_sel_cpsw 1>;
};
};
main_cpsw_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x0 0xf00 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 28 28>;
clock-names = "fck";
bus_freq = <1000000>;
};
cpts@3d000 {
compatible = "ti,am65-cpts";
reg = <0x0 0x3d000 0x0 0x400>;
clocks = <&k3_clks 28 3>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x04104000 0x00 0x100>;
clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
clock-names = "ref", "lpm";
assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 360 17>;
power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-coherent;
usb0: usb@6000000 {
compatible = "cdns,usb3";
reg = <0x00 0x06000000 0x00 0x10000>,
<0x00 0x06010000 0x00 0x10000>,
<0x00 0x06020000 0x00 0x10000>;
reg-names = "otg", "xhci", "dev";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host", "peripheral", "otg";
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
serdes_wiz0: wiz@5060000 {
compatible = "ti,j721e-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
num-lanes = <4>;
#reset-cells = <1>;
ranges = <0x5060000 0x0 0x5060000 0x10000>,
<0xa030a00 0x0 0xa030a00 0x40>; /* DPTX PHY */
assigned-clocks = <&k3_clks 365 3>;
assigned-clock-parents = <&k3_clks 365 7>;
wiz0_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 365 3>, <&serdes_refclk>;
clock-output-names = "wiz0_pll0_refclk";
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll0_refclk>;
assigned-clock-parents = <&k3_clks 365 3>;
};
wiz0_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 365 3>, <&serdes_refclk>;
clock-output-names = "wiz0_pll1_refclk";
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&k3_clks 365 3>;
};
wiz0_refclk_dig: refclk-dig {
clocks = <&k3_clks 365 3>, <&serdes_refclk>;
clock-output-names = "wiz0_refclk_dig";
#clock-cells = <0>;
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&k3_clks 365 3>;
};
wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
clocks = <&wiz0_refclk_dig>;
#clock-cells = <0>;
};
serdes0: serdes@5060000 {
/*
* Note: we also map DPTX PHY registers as the Torrent
* needs to manage those.
*/
compatible = "ti,j721e-serdes-10g";
reg = <0x05060000 0x00010000>,
<0xa030a00 0x40>; /* DPTX PHY */
reg-names = "torrent_phy", "dptx_phy";
resets = <&serdes_wiz0 0>;
reset-names = "torrent_reset";
clocks = <&wiz0_pll0_refclk>;
clock-names = "refclk";
#address-cells = <1>;
#size-cells = <0>;
torrent_phy_dp: phy@2 {
reg = <2>;
resets = <&serdes_wiz0 3>;
cdns,phy-type = <PHY_TYPE_DP>;
cdns,num-lanes = <2>;
cdns,max-bit-rate = <5400>;
#phy-cells = <0>;
};
};
};
pcie1_rc: pcie@2910000 {
compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
<0x00 0x18000000 0x00 0x00001000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 276 41>;
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb013>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
<0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
<0 0 0 2 &pcie1_intc 0>, /* INT B */
<0 0 0 3 &pcie1_intc 0>, /* INT C */
<0 0 0 4 &pcie1_intc 0>; /* INT D */
pcie1_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
};
};
pcie1_ep: pcie-ep@2910000 {
compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
<0x00 0x18000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 276 41>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
};
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
<0x5d00000 0x00 0x5d00000 0x20000>;
power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
main_r5fss0_core0: r5f@5c00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5c00000 0x00010000>,
<0x5c10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <279>;
ti,sci-proc-ids = <0x06 0xff>;
resets = <&k3_reset 279 1>;
firmware-name = "j721s2-main-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss0_core1: r5f@5d00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5d00000 0x00010000>,
<0x5d10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <280>;
ti,sci-proc-ids = <0x07 0xff>;
resets = <&k3_reset 280 1>;
firmware-name = "j721s2-main-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
main_r5fss1: r5fss@5e00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
<0x5f00000 0x00 0x5f00000 0x20000>;
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
main_r5fss1_core0: r5f@5e00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5e00000 0x00010000>,
<0x5e10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <281>;
ti,sci-proc-ids = <0x08 0xff>;
resets = <&k3_reset 281 1>;
firmware-name = "j721s2-main-r5f1_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss1_core1: r5f@5f00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5f00000 0x00010000>,
<0x5f10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <282>;
ti,sci-proc-ids = <0x09 0xff>;
resets = <&k3_reset 282 1>;
firmware-name = "j721s2-main-r5f1_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
c71_0: dsp@64800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x64800000 0x00 0x00080000>,
<0x00 0x64e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
ti,sci = <&sms>;
ti,sci-dev-id = <8>;
ti,sci-proc-ids = <0x30 0xff>;
resets = <&k3_reset 8 1>;
firmware-name = "j721s2-c71_0-fw";
};
c71_1: dsp@65800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x65800000 0x00 0x00080000>,
<0x00 0x65e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
ti,sci = <&sms>;
ti,sci-dev-id = <11>;
ti,sci-proc-ids = <0x31 0xff>;
resets = <&k3_reset 11 1>;
firmware-name = "j721s2-c71_1-fw";
};
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
<0x00 0x02708000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan1: can@2711000 {
compatible = "bosch,m_can";
reg = <0x00 0x02711000 0x00 0x200>,
<0x00 0x02718000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan2: can@2721000 {
compatible = "bosch,m_can";
reg = <0x00 0x02721000 0x00 0x200>,
<0x00 0x02728000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan3: can@2731000 {
compatible = "bosch,m_can";
reg = <0x00 0x02731000 0x00 0x200>,
<0x00 0x02738000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan4: can@2741000 {
compatible = "bosch,m_can";
reg = <0x00 0x02741000 0x00 0x200>,
<0x00 0x02748000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan5: can@2751000 {
compatible = "bosch,m_can";
reg = <0x00 0x02751000 0x00 0x200>,
<0x00 0x02758000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan6: can@2761000 {
compatible = "bosch,m_can";
reg = <0x00 0x02761000 0x00 0x200>,
<0x00 0x02768000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan7: can@2771000 {
compatible = "bosch,m_can";
reg = <0x00 0x02771000 0x00 0x200>,
<0x00 0x02778000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan8: can@2781000 {
compatible = "bosch,m_can";
reg = <0x00 0x02781000 0x00 0x200>,
<0x00 0x02788000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan9: can@2791000 {
compatible = "bosch,m_can";
reg = <0x00 0x02791000 0x00 0x200>,
<0x00 0x02798000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan10: can@27a1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027a1000 0x00 0x200>,
<0x00 0x027a8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan11: can@27b1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027b1000 0x00 0x200>,
<0x00 0x027b8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan12: can@27c1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027c1000 0x00 0x200>,
<0x00 0x027c8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan13: can@27d1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027d1000 0x00 0x200>,
<0x00 0x027d8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan14: can@2681000 {
compatible = "bosch,m_can";
reg = <0x00 0x02681000 0x00 0x200>,
<0x00 0x02688000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan15: can@2691000 {
compatible = "bosch,m_can";
reg = <0x00 0x02691000 0x00 0x200>,
<0x00 0x02698000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan16: can@26a1000 {
compatible = "bosch,m_can";
reg = <0x00 0x026a1000 0x00 0x200>,
<0x00 0x026a8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_mcan17: can@26b1000 {
compatible = "bosch,m_can";
reg = <0x00 0x026b1000 0x00 0x200>,
<0x00 0x026b8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
main_spi0: spi@2100000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02100000 0x00 0x400>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 339 1>;
power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
};
main_spi1: spi@2110000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02110000 0x00 0x400>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 340 1>;
power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
};
main_spi2: spi@2120000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02120000 0x00 0x400>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 341 1>;
power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
};
main_spi3: spi@2130000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02130000 0x00 0x400>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 342 1>;
power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
};
main_spi4: spi@2140000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02140000 0x00 0x400>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 343 1>;
power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
};
main_spi5: spi@2150000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02150000 0x00 0x400>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 344 1>;
power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
};
main_spi6: spi@2160000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02160000 0x00 0x400>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 345 1>;
power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
};
main_spi7: spi@2170000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02170000 0x00 0x400>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 346 1>;
power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
};
mhdp: dp-bridge@a000000 {
compatible = "ti,j721e-mhdp8546";
/*
* Note: we do not map DPTX PHY area, as that is handled by
* the PHY driver.
*/
reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
<0x0 0x4f40000 0x0 0x20>; /* DSS_EDP0_INTG_CFG_VP */
reg-names = "mhdptx", "j721e-intg";
clocks = <&k3_clks 156 19>;
phys = <&torrent_phy_dp>;
phy-names = "dpphy";
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
dp0_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
dphy0: phy@4480000 {
compatible = "ti,j721e-dphy";
reg = <0x0 0x04480000 0x0 0x1000>;
clocks = <&k3_clks 363 8>, <&k3_clks 363 14>;
clock-names = "psm", "pll_ref";
#phy-cells = <0>;
power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 363 14>;
assigned-clock-parents = <&k3_clks 363 15>;
assigned-clock-rates = <19200000>;
};
dsi0: dsi@4800000 {
compatible = "ti,j721e-dsi";
reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
clocks = <&k3_clks 154 4>, <&k3_clks 154 1>;
clock-names = "dsi_p_clk", "dsi_sys_clk";
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
phys = <&dphy0>;
phy-names = "dphy";
dsi0_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
};
};
dss: dss@4a00000 {
compatible = "ti,j721e-dss";
reg =
<0x00 0x04a00000 0x00 0x10000>, /* common_m */
<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
<0x00 0x04a60000 0x00 0x10000>, /* vid2 */
<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
<0x00 0x04af0000 0x00 0x10000>; /* wb */
reg-names = "common_m", "common_s0",
"common_s1", "common_s2",
"vidl1", "vidl2","vid1","vid2",
"ovr1", "ovr2", "ovr3", "ovr4",
"vp1", "vp2", "vp3", "vp4",
"wb";
clocks = <&k3_clks 158 0>,
<&k3_clks 158 2>,
<&k3_clks 158 5>,
<&k3_clks 158 14>,
<&k3_clks 158 18>;
clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common_m",
"common_s0",
"common_s1",
"common_s2";
dss_ports: ports {
};
};
ti_csi2rx0: ticsi2rx@4500000 {
compatible = "ti,j721e-csi2rx";
dmas = <&main_bcdma_csi 0 0x4940 0>, <&main_bcdma_csi 0 0x4941 0>,
<&main_bcdma_csi 0 0x4942 0>, <&main_bcdma_csi 0 0x4943 0>,
<&main_bcdma_csi 0 0x4944 0>, <&main_bcdma_csi 0 0x4945 0>,
<&main_bcdma_csi 0 0x4946 0>, <&main_bcdma_csi 0 0x4947 0>;
dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7";
reg = <0x00 0x04500000 0x00 0x1000>;
power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
cdns_csi2rx0: csi-bridge@4504000 {
compatible = "cdns,csi2rx";
reg = <0x00 0x04504000 0x00 0x1000>;
clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>,
<&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy_rx0>;
phy-names = "dphy";
power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
};
csi0_port1: port@1 {
reg = <1>;
};
csi0_port2: port@2 {
reg = <2>;
};
csi0_port3: port@3 {
reg = <3>;
};
csi0_port4: port@4 {
reg = <4>;
};
};
};
};
ti_csi2rx1: ticsi2rx@4510000 {
compatible = "ti,j721e-csi2rx";
dmas = <&main_bcdma_csi 0 0x4960 0>, <&main_bcdma_csi 0 0x4961 0>,
<&main_bcdma_csi 0 0x4962 0>, <&main_bcdma_csi 0 0x4963 0>,
<&main_bcdma_csi 0 0x4964 0>, <&main_bcdma_csi 0 0x4965 0>,
<&main_bcdma_csi 0 0x4966 0>, <&main_bcdma_csi 0 0x4967 0>;
dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7";
reg = <0x00 0x04510000 0x00 0x1000>;
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
cdns_csi2rx1: csi-bridge@4514000 {
compatible = "cdns,csi2rx";
reg = <0x00 0x04514000 0x00 0x1000>;
clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>,
<&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy_rx1>;
phy-names = "dphy";
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
ports {
#address-cells = <1>;
#size-cells = <0>;
csi1_port0: port@0 {
reg = <0>;
};
csi1_port1: port@1 {
reg = <1>;
};
csi1_port2: port@2 {
reg = <2>;
};
csi1_port3: port@3 {
reg = <3>;
};
csi1_port4: port@4 {
reg = <4>;
};
};
};
};
dphy_rx0: phy@4580000 {
compatible = "ti,j721e-dphy", "cdns,dphy";
reg = <0x00 0x04580000 0x00 0x1100>;
#phy-cells = <0>;
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
};
dphy_rx1: phy@4590000 {
compatible = "ti,j721e-dphy", "cdns,dphy";
reg = <0x00 0x04590000 0x00 0x1100>;
#phy-cells = <0>;
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
};
};
d. k3-j721s2-mcu-wakeup.dtsi
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu_wakeup {
sms: system-controller@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x00 0x1000>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
chipid@43000014 {
compatible = "ti,am654-chipid";
reg = <0x00 0x43000014 0x00 0x4>;
};
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
ranges = <0x00 0x00 0x41c00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
};
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x194>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x00 0x42200000 0x00 0x400>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <125>;
ti,interrupt-ranges = <16 960 16>;
};
mcu_conf: syscon@40f00000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x40f00000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40f00000 0x20000>;
phy_gmii_sel: phy@4040 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4040 0x4>;
#phy-cells = <1>;
};
};
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x200>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 359 3>;
clock-names = "fclk";
power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
};
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x200>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 149 3>;
clock-names = "fclk";
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
};
wkup_gpio0: gpio@42110000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x42110000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&wkup_gpio_intr>;
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <89>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 115 0>;
clock-names = "gpio";
};
wkup_gpio1: gpio@42100000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x42100000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&wkup_gpio_intr>;
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <89>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 116 0>;
clock-names = "gpio";
};
wkup_i2c0: i2c@42120000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x42120000 0x00 0x100>;
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 223 1>;
clock-names = "fck";
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
};
mcu_i2c0: i2c@40b00000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x40b00000 0x00 0x100>;
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 221 1>;
clock-names = "fck";
power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
};
mcu_i2c1: i2c@40b10000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x40b10000 0x00 0x100>;
interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 222 1>;
clock-names = "fck";
power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
};
mcu_mcan0: can@40528000 {
compatible = "bosch,m_can";
reg = <0x00 0x40528000 0x00 0x200>,
<0x00 0x40500000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
mcu_mcan1: can@40568000 {
compatible = "bosch,m_can";
reg = <0x00 0x40568000 0x00 0x200>,
<0x00 0x40540000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
mcu_spi0: spi@40300000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x040300000 0x00 0x400>;
interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 347 0>;
};
mcu_spi1: spi@40310000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x040310000 0x00 0x400>;
interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 348 0>;
};
mcu_spi2: spi@40320000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x040320000 0x00 0x400>;
interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 349 0>;
};
mcu_navss: bus@28380000{
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
dma-coherent;
dma-ranges;
ti,sci-dev-id = <267>;
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
ti,sci-dev-id = <272>;
msi-parent = <&main_udmass_inta>;
};
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <273>;
ti,ringacc = <&mcu_ringacc>;
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
<0x0f>; /* TX_HCHAN */
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
};
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x46000000 0x0 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
dma-coherent;
clocks = <&k3_clks 29 28>;
clock-names = "fck";
power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
dmas = <&mcu_udmap 0xf000>,
<&mcu_udmap 0xf001>,
<&mcu_udmap 0xf002>,
<&mcu_udmap 0xf003>,
<&mcu_udmap 0xf004>,
<&mcu_udmap 0xf005>,
<&mcu_udmap 0xf006>,
<&mcu_udmap 0xf007>,
<&mcu_udmap 0x7000>;
dma-names = "tx0", "tx1", "tx2", "tx3",
"tx4", "tx5", "tx6", "tx7",
"rx";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
label = "port1";
ti,syscon-efuse = <&mcu_conf 0x200>;
phys = <&phy_gmii_sel 1>;
};
};
davinci_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x0 0xf00 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 29 28>;
clock-names = "fck";
bus_freq = <1000000>;
};
cpts@3d000 {
compatible = "ti,am65-cpts";
reg = <0x0 0x3d000 0x0 0x400>;
clocks = <&k3_clks 29 3>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
fss: syscon@47000000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x47000000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x47040000 0x00 0x100>,
<0x5 0x0000000 0x1 0x0000000>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 109 5>;
assigned-clocks = <&k3_clks 109 5>;
assigned-clock-parents = <&k3_clks 109 7>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
ospi1: spi@47050000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x47050000 0x00 0x100>,
<0x7 0x0000000 0x1 0x0000000>;
interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 110 5>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
};
tscadc0: tscadc@40200000 {
compatible = "ti,am3359-tscadc";
reg = <0x0 0x40200000 0x0 0x1000>;
interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 0 0>;
assigned-clocks = <&k3_clks 0 2>;
assigned-clock-rates = <60000000>;
clock-names = "adc_tsc_fck";
dmas = <&main_udmap 0x7400>,
<&main_udmap 0x7401>;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
compatible = "ti,am3359-adc";
};
};
tscadc1: tscadc@40210000 {
compatible = "ti,am3359-tscadc";
reg = <0x0 0x40210000 0x0 0x1000>;
interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 1 0>;
assigned-clocks = <&k3_clks 1 2>;
assigned-clock-rates = <60000000>;
clock-names = "adc_tsc_fck";
dmas = <&main_udmap 0x7402>,
<&main_udmap 0x7403>;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
compatible = "ti,am3359-adc";
};
};
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
<0x41400000 0x00 0x41400000 0x20000>;
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
mcu_r5fss0_core0: r5f@41000000 {
compatible = "ti,j721s2-r5f";
reg = <0x41000000 0x00010000>,
<0x41010000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <284>;
ti,sci-proc-ids = <0x01 0xff>;
resets = <&k3_reset 284 1>;
firmware-name = "j721s2-mcu-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
mcu_r5fss0_core1: r5f@41400000 {
compatible = "ti,j721s2-r5f";
reg = <0x41400000 0x00010000>,
<0x41410000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <285>;
ti,sci-proc-ids = <0x02 0xff>;
resets = <&k3_reset 285 1>;
firmware-name = "j721s2-mcu-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
wkup_vtm0: temperature-sensor@42040000 {
compatible = "ti,j7200-vtm";
reg = <0x0 0x42040000 0x0 0x350>,
<0x0 0x42050000 0x0 0x350>,
<0x0 0x43000300 0x0 0x10>;
power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
};
};
e. k3-j721s2-rtos-memory-map.dtsi
// SPDX-License-Identifier: GPL-2.0
/*
* Vision-apps: device-tree overlay
*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
dma_buf_phys {
compatible = "ti,dma-buf-phys";
};
};
&mcu_r5fss0_core0_memory_region {
status = "disabled";
};
&mcu_r5fss0_core0_dma_memory_region {
status = "disabled";
};
&mcu_r5fss0_core1_dma_memory_region {
status = "disabled";
};
&mcu_r5fss0_core1_memory_region {
status = "disabled";
};
&main_r5fss0_core0_dma_memory_region {
status = "disabled";
};
&main_r5fss0_core0_memory_region {
status = "disabled";
};
&main_r5fss0_core1_dma_memory_region {
status = "disabled";
};
&main_r5fss0_core1_memory_region {
status = "disabled";
};
&main_r5fss1_core0_dma_memory_region {
status = "disabled";
};
&main_r5fss1_core0_memory_region {
status = "disabled";
};
&main_r5fss1_core1_dma_memory_region {
status = "disabled";
};
&main_r5fss1_core1_memory_region {
status = "disabled";
};
&c71_0_dma_memory_region {
status = "disabled";
};
&c71_0_memory_region {
status = "disabled";
};
&c71_1_dma_memory_region {
status = "disabled";
};
&c71_1_memory_region {
status = "disabled";
};
&rtos_ipc_memory_region {
status = "disabled";
};
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
vision_apps_mcu_r5fss0_core0_dma_memory_region: vision-apps-r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x00100000>;
no-map;
};
vision_apps_mcu_r5fss0_core0_memory_region: vision-apps-r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0x00f00000>;
no-map;
};
vision_apps_mcu_r5fss0_core1_dma_memory_region: vision-apps-r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x00100000>;
no-map;
};
vision_apps_mcu_r5fss0_core1_memory_region: vision-apps-r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0x00f00000>;
no-map;
};
vision_apps_main_r5fss0_core0_dma_memory_region: vision-apps-r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x00100000>;
no-map;
};
vision_apps_main_r5fss0_core0_memory_region: vision-apps-r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0x01f00000>;
no-map;
};
vision_apps_main_r5fss0_core1_dma_memory_region: vision-apps-r5f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x00100000>;
no-map;
};
vision_apps_main_r5fss0_core1_memory_region: vision-apps-r5f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0x01f00000>;
no-map;
};
vision_apps_main_r5fss1_core0_dma_memory_region: vision-apps-r5f-dma-memory@a6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6000000 0x00 0x00100000>;
no-map;
};
vision_apps_main_r5fss1_core0_memory_region: vision-apps-r5f-memory@a6100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6100000 0x00 0x00f00000>;
no-map;
};
vision_apps_main_r5fss1_core1_dma_memory_region: vision-apps-r5f-dma-memory@a7000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7000000 0x00 0x00100000>;
no-map;
};
vision_apps_main_r5fss1_core1_memory_region: vision-apps-r5f-memory@a7100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7100000 0x00 0x00f00000>;
no-map;
};
vision_apps_rtos_ipc_memory_region: vision-apps-rtos-ipc-memory-region@a8000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa8000000 0x00 0x02000000>;
no-map;
};
vision_apps_memory_region: vision-apps-dma-memory@aa000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xaa000000 0x00 0x06000000>;
no-map;
};
vision_apps_c71_0_dma_memory_region: vision-apps-c71-dma-memory@b0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xb0000000 0x00 0x00100000>;
no-map;
};
vision_apps_c71_0_memory_region: vision-apps-c71_0-memory@b0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xb0100000 0x00 0x05f00000>;
no-map;
};
vision_apps_c71_1_dma_memory_region: vision-apps-c71_1-dma-memory@b6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xb6000000 0x00 0x00100000>;
no-map;
};
vision_apps_c71_1_memory_region: vision-apps-c71_1-memory@b6100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xb6100000 0x00 0x01f00000>;
no-map;
};
vision_apps_shared_region: vision_apps_shared-memories {
compatible = "dma-heap-carveout";
reg = <0x00 0xb8000000 0x00 0x20000000>;
};
vision_apps_core_heaps_lo: vision-apps-core-heap-memory-lo@d8000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xd8000000 0x00 0x04000000>;
no-map;
};
vision_apps_core_heaps_hi: vision-apps-core-heap-memory-hi@880000000 {
compatible = "shared-dma-pool";
reg = <0x08 0x80000000 0x00 0x2c000000>;
no-map;
};
zx_app_shared_region: zx-app-shared-memories {
compatible = "dma-heap-carveout";
reg = <0x00 0xdc000000 0x00 0x01000000>;
alignment = <0x1000>;
};
zx_ota_shared_region: zx-ota-shared-memories {
compatible = "dma-heap-carveout";
reg = <0x00 0xdd000000 0x00 0x03000000>;
alignment = <0x1000>;
};
/*add fast transfer channel for AEB function*/
zx_ftc_shared_region: zx-ftc-shared-memories {
compatible = "dma-heap-carveout";
reg = <0x00 0xe0000000 0x00 0x00010000>;
alignment = <0x1000>;
};
/*add transfer channel for config coding function*/
zx_ccw_shared_region: zx-ccw-shared-memories {
compatible = "dma-heap-carveout";
reg = <0x00 0xe0010000 0x00 0x00010000>;
alignment = <0x1000>;
};
};
&mcu_r5fss0_core0 {
memory-region = <&vision_apps_mcu_r5fss0_core0_dma_memory_region>,
<&vision_apps_mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
memory-region = <&vision_apps_mcu_r5fss0_core1_dma_memory_region>,
<&vision_apps_mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
memory-region = <&vision_apps_main_r5fss0_core0_dma_memory_region>,
<&vision_apps_main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
memory-region = <&vision_apps_main_r5fss0_core1_dma_memory_region>,
<&vision_apps_main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
memory-region = <&vision_apps_main_r5fss1_core0_dma_memory_region>,
<&vision_apps_main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
memory-region = <&vision_apps_main_r5fss1_core1_dma_memory_region>,
<&vision_apps_main_r5fss1_core1_memory_region>;
};
&c71_0 {
memory-region = <&vision_apps_c71_0_dma_memory_region>,
<&vision_apps_c71_0_memory_region>;
};
&c71_1 {
memory-region = <&vision_apps_c71_1_dma_memory_region>,
<&vision_apps_c71_1_memory_region>;
};
f.k3-j721s2-som-p0.dtsi
// SPDX-License-Identifier: GPL-2.0
/*
* SoM: https://www.ti.com/lit/zip/sprr439
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-j721s2.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
memory@80000000 {
device_type = "memory";
/* 16 GB RAM */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x00 0x80000000>;
};
/* Reserving memory regions still pending */
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
alignment = <0x1000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5100000 0x00 0xf00000>;
no-map;
};
c71_0_dma_memory_region: c71-dma-memory@a6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6000000 0x00 0x100000>;
no-map;
};
c71_0_memory_region: c71-memory@a6100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6100000 0x00 0xf00000>;
no-map;
};
c71_1_dma_memory_region: c71-dma-memory@a7000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7000000 0x00 0x100000>;
no-map;
};
c71_1_memory_region: c71-memory@a7100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a8000000 {
reg = <0x00 0xa8000000 0x00 0x01c00000>;
alignment = <0x1000>;
no-map;
};
};
mux0: mux-controller0 {
compatible = "gpio-mux";
#mux-state-cells = <1>;
mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
};
mux1: mux-controller1 {
compatible = "gpio-mux";
#mux-state-cells = <1>;
mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
};
transceiver0: can-phy0 {
/* standby pin has been grounded by default */
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
};
vsys_io_1v8: regulator-vsys-io-1v8 {
compatible = "regulator-fixed";
regulator-name = "vsys_io_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
vsys_io_1v2: regulator-vsys-io-1v2 {
compatible = "regulator-fixed";
regulator-name = "vsys_io_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
edp1_refclk: clock-edp1-refclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <19200000>;
};
};
&wkup_pmx0 {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */
J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */
J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */
J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
>;
};
};
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
>;
};
main_mcan16_pins_default: main-mcan16-pins-default {
pinctrl-single,pins = <
J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
>;
};
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
exp_som: gpio@21 {
compatible = "ti,tca6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
"CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
"GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
"GPIO_LIN_EN", "CAN_STB";
};
};
&main_mcan16 {
pinctrl-0 = <&main_mcan16_pins_default>;
pinctrl-names = "default";
phys = <&transceiver0>;
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&mailbox0_cluster0 {
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster1 {
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster2 {
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_c71_1: mbox-c71-1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
status = "disabled";
};
&mailbox0_cluster7 {
status = "disabled";
};
&mailbox0_cluster8 {
status = "disabled";
};
&mailbox0_cluster9 {
status = "disabled";
};
&mailbox0_cluster10 {
status = "disabled";
};
&mailbox0_cluster11 {
status = "disabled";
};
&mailbox1_cluster0 {
status = "disabled";
};
&mailbox1_cluster1 {
status = "disabled";
};
&mailbox1_cluster2 {
status = "disabled";
};
&mailbox1_cluster3 {
status = "disabled";
};
&mailbox1_cluster4 {
status = "disabled";
};
&mailbox1_cluster5 {
status = "disabled";
};
&mailbox1_cluster6 {
status = "disabled";
};
&mailbox1_cluster7 {
status = "disabled";
};
&mailbox1_cluster8 {
status = "disabled";
};
&mailbox1_cluster9 {
status = "disabled";
};
&mailbox1_cluster10 {
status = "disabled";
};
&mailbox1_cluster11 {
status = "disabled";
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c71_0 {
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
&c71_1 {
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
memory-region = <&c71_1_dma_memory_region>,
<&c71_1_memory_region>;
};
&main_i2c4 {
dsi_edp_bridge: dsi-edp-bridge@2c {
compatible = "ti,sn65dsi86";
reg = <0x2c>;
clock-names = "refclk";
clocks = <&edp1_refclk>;
enable-gpios = <&exp_som 5 0>;
vpll-supply = <&vsys_io_1v8>;
vccio-supply = <&vsys_io_1v8>;
vcca-supply = <&vsys_io_1v2>;
vcc-supply = <&vsys_io_1v2>;
dsi_edp_bridge_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
};
};
};
g. k3-j721s2.dtsi
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721S2 SoC Family
*
* TRM (SPRUJ28 â NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 J721S2 SoC";
compatible = "ti,j721s2";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a72";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a72";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_0>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
next-level-cache = <&msmc_l3>;
};
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
a72_timer0: timer-cl0-cpu0 {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
};
pmu: pmu {
compatible = "arm,cortex-a72-pmu";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
cbass_main: bus@100000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
<0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
/* MCUSS_WKUP Range */
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
cbass_mcu_wakeup: bus@28380000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
};
};
};
/* Now include peripherals from each bus segment */
#include "k3-j721s2-main.dtsi"
#include "k3-j721s2-mcu-wakeup.dtsi"
Hi Jared,
I do the test this not running mcu10, A core wkup_gpio0 driver init interrupts is succeed.
mcu10 also used the two pin of wkup_gpio0 as interrupts gpio, is this influence the A core wkup_gpio0 register interrupts ?
Hi,
It looks like you may have a conflict. If you're defining the pinmux for a pin in two different locations at the same time, you'll run into issues. You need to disable one.
Best,
Jared
Hi Jared,
MCU10 need used WKUP_GPIO0_5 as interrupts pin ,and A core need used WKUP_GPIO0_14 as interrupts pin，this can lead to conflicts。
WKUP_GPIO0_5 and WKUP_GPIO0_14 in a set of interrupts source. I don't want to change the hardware .What can be done to solve this problem?
Hi,
Are you trying to use two different functions on the pins? If not, simply remove/disable the unused function from the device tree.
Best,
Jared