DMA to SD Card in EzDSP 5515

Hi Friends ...

I have tried setting up DMA to the SD Card following the CSL_MMCSD_dmaExample (CSL low power 2.50). With the code, I can understand these sequence of events happening when DMA is started for SD Card Read/Write with callback

1. Read / Write initiated using mmc_read or mmc_write function.
2. After starting the DMA data transfer is started mmc_read or mmc_write calls mmcsdTransferDoneCallBack
3. mmcsdTransferDoneCallBack could wait for data transfer to complete which is indicated by an interrupt (ISR)
4. after the callback function complete execution (Say after waiting for the transfer to complete), control goes back to the main function from where mmc_read or mmc_write was executed.

If I measure the clock cycle used between step 1 and step 4 using a separate GPT counter set to run at 1/4th the CPU speed (100 MHz)

    status = GPT_getCnt(hGpt, &timeCnt1);
    mmcStatus = MMC_write(mmcsdHandle, cardAddr, BUFFER_MAX_SIZE,
                            gWriteTempBuff);
    status = GPT_getCnt(hGpt, &timeCnt2);
    cycle=(timeCnt1-timeCnt2)*4;

I get these results

563152 - Cycles spent for complete transfer and next statement execution (Write)
113212 - Cycles spent for complete transfer and next statement execution (Read)

This is nearly 1/2 a million clock cycles for write operation using DMA to write only 512 bytes.

So, instead I tried measuring clock cycles between step 1 and step 2 above, I got these results. 

14668 - Clock cycle to set up DMA (Write)
1788 - Clock Cycle to set up DMA (Read)

Also, the time taken in step 3 are

32616 - Clock Cycle used for waiting for the data transfer - Write
97428 - Clock cycle used for waiting for the data transfer - read

I cannot understand such huge number of clock cycles used in step 4.

My requirement is to write real time data of size 3.2 Kilo Bytes in 10 msec.

So, I have these two questions

1. Can I do more than 512 byte transfer using DMA on one go? (I changed the example code for the same, but read and write buffer mismatches at 512 address)
2. I cannot understand such huge number of clock cycles used in step 4. (563K-14K-32K) = 500K. So, should I initiate my next DMA just after step 3 ?

It would be highly helpful if somebody tells if things could work this way. My engineering says that DMA should work and saves precious CPU cycle, but this precise what is not happening.

Thanks and regards