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How to use L2 cache on C6678?

helloti
Prodigy 180 points
Other Parts Discussed in Thread: SYSBIOS

I use L2 cache on C6678 failed

Configuration & environment
    CCS            5.0.3
    SYS/BIOS       2.00.02.14
    little-endian
    NDK            ndk_2_20_04_26

    TCP connect by DaemonNew( SOCK_STREAMNC, ...);
    All program section map to DDR3

Problem
    Connect TCP link by using NDK. Then send data to PC repeated, send 200k byte each time.
    If I configured the Cache and ran in this way for a while, the error message would be output as follow, and the link can't be connected again.
    [C66xx_0] 00027.648 PBM_free: Invalid Packet
    [C66xx_0] 00027.649 mmFree: Double Free
    [C66xx_0] 00027.650 PBM_enq: Invalid Packet
    [C66xx_0] Network Removed: If-1:192.168.0.55
    [C66xx_0] 00027.652 PBM_free: Invalid Packet
    [C66xx_0] 00027.653 mmFree: Double Free
    [C66xx_0] 00027.654 mmFree: Double Free
    [C66xx_0] 00027.655 mmFree: Double Free
    [C66xx_0] 00027.656 mmFree: Double Free
    [C66xx_0] 00027.657 mmFree: Double Free
    [C66xx_0] 00027.658 mmFree: Double Free
    [C66xx_0] 00027.659 mmBulkFree: Corrupted mem or bad ptr (8020b028)
    [C66xx_0] 00027.660 mmFree: Double Free
    [C66xx_0] 00027.661 mmFree: Double Free
    [C66xx_0] ti.sysbios.heaps.HeapMem: line 331: assertion failure: A_invalidFree: Invalid free
    [C66xx_0] xdc.runtime.Error.raise: terminating execution

But, if the Cache is not configured, it can run correctly.

    I configured the Cache by two method, both of them can cause the same problem as above. One way is configuring cache by using RTSC tools, the other way is using the following code:
    CACHE_enableCaching(128);
    CACHE_enableCaching(129);
    CACHE_enableCaching(130);
    CACHE_enableCaching(131);
    CACHE_enableCaching(132);
    CACHE_enableCaching(133);
    CACHE_enableCaching(134);
    CACHE_enableCaching(135);
    CACHE_enableCaching(136);
    CACHE_enableCaching(137);
    CACHE_enableCaching(138);
    CACHE_enableCaching(139);
    CACHE_enableCaching(140);
    CACHE_enableCaching(141);
    CACHE_enableCaching(142);
    CACHE_enableCaching(143);
    CACHE_setL2Size(CACHE_256KCACHE);

So, would you please how to config cache correctly?

  • 0
    TI__Mastermind 23525 points

    Did you figure out the issue you were facing here?  My guess is that the problem is not how you enable the cache, but how it is being used.  Are you performing the necessary invalidate commands prior to reading from DDR and the necessary write-back commands when writing to the cached memory addresses?

     

    Regards,

    Travis