TDA4VL-Q1: MCU DDR access priority

Xingyu Zhu

Part Number: TDA4VL-Q1
Other Parts Discussed in Thread: TDA4VL, TDA4VM

Tool/software:

Hi expert,

Our customer is using TDA4VL SDK0806. They found the operation of MAIN domain will impact the MCU1_0 task cycle and the issue disappear when moving the MCU code to MSMC. So they suspect this is caused by the priority of DDR access.

They also test the DDR bandwidth by the ti perf. The actual bandwidth is below 8GB/s. So we think the DDR bandwidth still have some buffer. They once used TDA4VM SDK7.3 and didn't run into similar issue.

They referd to below 2 thread and added the NB and QoS config for the MCU, but it didn't work.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1214683/faq-processor-sdk-j721s2-how-to-enable-qos-for-dss-in-sbl-or-in-spl-boot-flow?tisearch=e2e-sitesearch&keymatch=SBL%20QOS

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1225862/tda4vl-evm-data-captured-by-dma-timer-p-is-missing-or-unable-to-be-captured/4653418#4653418

As shown in the below diagram, there are CBASS, NAVSS, MSMC and DDSS, and DDRSS is only connected to MSMC. Customer would like to know:

1. Regarding the above 2 patches, what is the function of NB and QoS config? Can it help MCU access DDR?

2. Besides the QoS, it there any other points they need to care and check?

Best Regards,

Xingyu Zhu

over 1 year ago

0 Brijesh Jadav over 1 year ago

TI__Guru**** 477995 points

Hi Xingyu,

Xingyu Zhu said:
They once used TDA4VM SDK7.3 and didn't run into similar issue.

this is strange, are you sure that they did not see issue on SDK7.3? Because then it may not be related to QoS, because SDK7.3 did not support QoS parameter setting for TDA4VL..

Also in the second link, i think i had provided the QoS settings for mcu3_0, not for mcu1_0. Does customer change it to support mcu1_0?

Regards,

Brijesh

0 Xingyu Zhu over 1 year ago in reply to Brijesh Jadav

TI__Expert 4335 points

Hi Brijesh,

Thanks for your reply.

Brijesh Jadav said:
this is strange, are you sure that they did not see issue on SDK7.3? Because then it may not be related to QoS, because SDK7.3 did not support QoS parameter setting for TDA4VL.

Customer didn't see this issue on TDA4VM SDK7.3, not VL. 7.3 VM should have QoS setting in the SBL.

Brijesh Jadav said:
i think i had provided the QoS settings for mcu3_0, not for mcu1_0. Does customer change it to support mcu1_0?

They add below setting. The default MCU1_0 QoS setting is 0x7000, they changed it to 0x70C0.

0 Brijesh Jadav over 1 year ago in reply to Xingyu Zhu

TI__Guru**** 477995 points

Hi Xingyu,

This looks to be correct change. What issue are you seeing with this change? Are you not able to access the register or something else?

Regards,

Brijesh

0 Xingyu Zhu over 1 year ago in reply to Brijesh Jadav

TI__Expert 4335 points

Hi Brijesh,

Customer found this change cannot resolve their issue that MCU CAN cycle time is not stable (the operation of Main domain will impact the MCU DDR access). If they move the code to the internal RAM, this issue can get resolved. But the internal RAM size is not enough, so they want to increase the MCU DDR access priority.

0 Brijesh Jadav over 1 year ago in reply to Xingyu Zhu

TI__Guru**** 477995 points

Hi Xingyu,

This change will give priority to MCU R5F, but cannot guarantee the BW. So first we need to understand what all things are running on the main domain? Are they generating heavy DDR BW? Are C7x and A72 also involved in the usecase?

Regards,

Brijesh

0 Yongzheng Shi over 1 year ago in reply to Brijesh Jadav

Prodigy 10 points

Hi Brijesh,

C7x and A72 also involved in this usecase. When the MCU1_0 code is located at DDR, if we not run C7x, the DDR BW is about 1GB/s, and the MCU1_0 CAN cycle is stable. If we run the C7x, the BW go up to about 8GB/s, and the MCU1_0 CAN cycle is not stable any more.

Regards,

Yongzheng

0 Brijesh Jadav over 1 year ago in reply to Yongzheng Shi

TI__Guru**** 477995 points

Hi Yongzheng Shi,

Can you please try changing value in this register to 0x300070C0?

Regards,

Brijesh

0 Gaston yan over 1 year ago in reply to Brijesh Jadav

Intellectual 545 points

Hi Brijesh:

We also tested the dma consistency type a few days ago, but it didn't work. I'll post the entire file here to see if there's any improvement. We didn't encounter this problem before using TDA4VM sdk0703, but now we have this problem using TDA4AL 0806sdk. Please help analyze it.

The file I changed is here

Fullscreen sbl_qos_j721s2.c Download

/*
 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * Redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer.
 *
 * Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the
 * distribution.
 *
 * Neither the name of Texas Instruments Incorporated nor the names of
 * its contributors may be used to endorse or promote products derived
 * from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#include <stdint.h>
#include <ti/csl/cslr.h>
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>

#if defined(SOC_J721S2)

#define QOS_C66SS0_MDMA_ATYPE                (0U)
#define QOS_C66SS1_MDMA_ATYPE                (0U)
#define QOS_VPAC0_DATA0_ATYPE                (0U)
#define QOS_VPAC0_DATA1_ATYPE                (0U)
#define QOS_VPAC0_LDC0_ATYPE                 (0U)
#define QOS_DMPAC0_DATA_ATYPE                (0U)
#define QOS_DSS0_DMA_ATYPE                   (3U)
#define QOS_DSS0_FBDC_ATYPE                  (0U)
#define QOS_GPU0_M0_RD_ATYPE                 (0U)
#define QOS_GPU0_M0_WR_ATYPE                 (0U)
#define QOS_GPU0_M1_RD_ATYPE                 (0U)
#define QOS_GPU0_M1_WR_ATYPE                 (0U)
#define QOS_ENCODER0_RD_ATYPE                (0U)
#define QOS_ENCODER0_WR_ATYPE                (0U)
#define QOS_DECODER0_RD_ATYPE                (0U)
#define QOS_DECODER0_WR_ATYPE                (0U)
#define QOS_R5FSS0_CORE0_MEM_RD_ATYPE        (0U)
#define QOS_R5FSS0_CORE0_MEM_WR_ATYPE        (0U)
#define QOS_R5FSS0_CORE1_MEM_RD_ATYPE        (0U)
#define QOS_R5FSS0_CORE1_MEM_WR_ATYPE        (0U)

#define QOS_VPAC0_LDC0_ORDER_ID              (1U)
#define QOS_C66SS0_MDMA_ORDER_ID             (5U)
#define QOS_C66SS1_MDMA_ORDER_ID             (5U)
#define QOS_ENCODER0_RD_ORDER_ID             (6U)
#define QOS_ENCODER0_WR_ORDER_ID             (6U)
#define QOS_DECODER0_RD_ORDER_ID             (6U)
#define QOS_DECODER0_WR_ORDER_ID             (6U)
#define QOS_GPU0_M0_RD_ORDER_ID              (7U)
#define QOS_GPU0_M0_WR_ORDER_ID              (7U)
#define QOS_GPU0_M1_RD_ORDER_ID              (7U)
#define QOS_GPU0_M1_WR_ORDER_ID              (7U)
#define QOS_DSS0_DMA_ORDER_ID                (15U)
#define QOS_DSS0_FBDC_ORDER_ID               (10U)
#define QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID     (11U)
#define QOS_R5FSS0_CORE0_MEM_WR_ORDER_ID     (11U)
#define QOS_R5FSS0_CORE1_MEM_RD_ORDER_ID     (11U)
#define QOS_R5FSS0_CORE1_MEM_WR_ORDER_ID     (11U)
#define QOS_R5FSS1_CORE0_MEM_RD_ORDER_ID     (11U)
#define QOS_R5FSS1_CORE0_MEM_WR_ORDER_ID     (11U)

#define QOS_DSS0_DMA_PRIORITY                (1U)
#define QOS_DSS0_FBDC_PRIORITY               (1U)
#define QOS_VPAC0_LDC0_PRIORITY              (3U)
#define QOS_C66SS0_MDMA_PRIORITY             (5U)
#define QOS_C66SS1_MDMA_PRIORITY             (5U)
#define QOS_ENCODER0_RD_PRIORITY             (6U)
#define QOS_ENCODER0_WR_PRIORITY             (6U)
#define QOS_DECODER0_RD_PRIORITY             (6U)
#define QOS_DECODER0_WR_PRIORITY             (6U)
#define QOS_GPU0_M0_RD_MMU_PRIORITY          (3U)
#define QOS_GPU0_M0_RD_PRIORITY              (7U)
#define QOS_GPU0_M0_WR_PRIORITY              (7U)
#define QOS_GPU0_M1_RD_PRIORITY              (7U)
#define QOS_GPU0_M1_RD_MMU_PRIORITY          (3U)
#define QOS_GPU0_M1_WR_PRIORITY              (7U)
#define QOS_R5FSS0_CORE0_MEM_RD_PRIORITY     (7U)
#define QOS_R5FSS0_CORE0_MEM_WR_PRIORITY     (7U)
#define QOS_R5FSS0_CORE1_MEM_RD_PRIORITY     (7U)
#define QOS_R5FSS0_CORE1_MEM_WR_PRIORITY     (7U)

#define QOS_ATYPE_MASK         0x30000000
#define QOS_VIRTID_MASK            0x0fff0000
#define QOS_PVU_CTX(virtid)        ((0x1 << 28) | (virtid << 16))
#define QOS_SMMU_CTX(virtid)       ((0x2 << 28) | (virtid << 16))

/* CBASS */

#define QOS_C66SS0_MDMA                             0x45d81000
#define QOS_C66SS0_MDMA_NUM_J_CH                    3
#define QOS_C66SS0_MDMA_NUM_I_CH                    1
#define QOS_C66SS0_MDMA_CBASS_GRP_MAP1(j)           (QOS_C66SS0_MDMA + 0x0 + (j) * 8)
#define QOS_C66SS0_MDMA_CBASS_GRP_MAP2(j)           (QOS_C66SS0_MDMA + 0x4 + (j) * 8)
#define QOS_C66SS0_MDMA_CBASS_MAP(i)                (QOS_C66SS0_MDMA + 0x100 + (i) * 4)

#define QOS_C66SS1_MDMA                             0x45d81400
#define QOS_C66SS1_MDMA_NUM_J_CH                    3
#define QOS_C66SS1_MDMA_NUM_I_CH                    1
#define QOS_C66SS1_MDMA_CBASS_GRP_MAP1(j)           (QOS_C66SS1_MDMA + 0x0 + (j) * 8)
#define QOS_C66SS1_MDMA_CBASS_GRP_MAP2(j)           (QOS_C66SS1_MDMA + 0x4 + (j) * 8)
#define QOS_C66SS1_MDMA_CBASS_MAP(i)                (QOS_C66SS1_MDMA + 0x100 + (i) * 4)

#define QOS_R5FSS0_CORE0_MEM_RD                     0x45d78000
#define QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH            3
#define QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH            1
#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(j)   (QOS_R5FSS0_CORE0_MEM_RD + 0x0 + (j) * 8)
#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(j)   (QOS_R5FSS0_CORE0_MEM_RD + 0x4 + (j) * 8)
#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(i)        (QOS_R5FSS0_CORE0_MEM_RD + 0x100 + (i) * 4)

#define QOS_R5FSS0_CORE1_MEM_RD                     0x45d78400
#define QOS_R5FSS0_CORE1_MEM_RD_NUM_J_CH            3
#define QOS_R5FSS0_CORE1_MEM_RD_NUM_I_CH            1
#define QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(j)   (QOS_R5FSS0_CORE1_MEM_RD + 0x0 + (j) * 8)
#define QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(j)   (QOS_R5FSS0_CORE1_MEM_RD + 0x4 + (j) * 8)
#define QOS_R5FSS0_CORE1_MEM_RD_CBASS_MAP(i)        (QOS_R5FSS0_CORE1_MEM_RD + 0x100 + (i) * 4)

#define QOS_R5FSS0_CORE0_MEM_WR                     0x45d78800
#define QOS_R5FSS0_CORE0_MEM_WR_NUM_J_CH            3
#define QOS_R5FSS0_CORE0_MEM_WR_NUM_I_CH            1
#define QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(j)   (QOS_R5FSS0_CORE0_MEM_WR + 0x0 + (j) * 8)
#define QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(j)   (QOS_R5FSS0_CORE0_MEM_WR + 0x4 + (j) * 8)
#define QOS_R5FSS0_CORE0_MEM_WR_CBASS_MAP(i)        (QOS_R5FSS0_CORE0_MEM_WR + 0x100 + (i) * 4)

#define QOS_R5FSS0_CORE1_MEM_WR                     0x45d78c00
#define QOS_R5FSS0_CORE1_MEM_WR_NUM_J_CH            3
#define QOS_R5FSS0_CORE1_MEM_WR_NUM_I_CH            1
#define QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(j)   (QOS_R5FSS0_CORE1_MEM_WR + 0x0 + (j) * 8)
#define QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(j)   (QOS_R5FSS0_CORE1_MEM_WR + 0x4 + (j) * 8)
#define QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(i)        (QOS_R5FSS0_CORE1_MEM_WR + 0x100 + (i) * 4)

#define QOS_R5FSS1_CORE0_MEM_RD                     0x45d79000

#define QOS_R5FSS1_CORE0_MEM_RD_NUM_J_CH            3

#define QOS_R5FSS1_CORE0_MEM_RD_NUM_I_CH            1

#define QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP1(j)   (QOS_R5FSS1_CORE0_MEM_RD + 0x0 + (j) * 8)

#define QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP2(j)   (QOS_R5FSS1_CORE0_MEM_RD + 0x4 + (j) * 8)

#define QOS_R5FSS1_CORE0_MEM_RD_CBASS_MAP(i)        (QOS_R5FSS1_CORE0_MEM_RD + 0x100 + (i) * 4)



#define QOS_R5FSS1_CORE0_MEM_WR                     0x45d85800

#define QOS_R5FSS1_CORE0_MEM_WR_NUM_J_CH            3

#define QOS_R5FSS1_CORE0_MEM_WR_NUM_I_CH            1

#define QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP1(j)   (QOS_R5FSS1_CORE0_MEM_WR + 0x0 + (j) * 8)

#define QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP2(j)   (QOS_R5FSS1_CORE0_MEM_WR + 0x4 + (j) * 8)

#define QOS_R5FSS1_CORE0_MEM_WR_CBASS_MAP(i)        (QOS_R5FSS1_CORE0_MEM_WR + 0x100 + (i) * 4)



#define QOS_R5FSS1_CORE0_MEM_RD_PRIORITY     (2U)

#define QOS_R5FSS1_CORE0_MEM_WR_PRIORITY     (2U)

#define QOS_ENCODER0_WR                             0x45dc1000
#define QOS_ENCODER0_WR_NUM_J_CH                    2
#define QOS_ENCODER0_WR_NUM_I_CH                    5
#define QOS_ENCODER0_WR_CBASS_GRP_MAP1(j)           (QOS_ENCODER0_WR + 0x0 + (j) * 8)
#define QOS_ENCODER0_WR_CBASS_GRP_MAP2(j)           (QOS_ENCODER0_WR + 0x4 + (j) * 8)
#define QOS_ENCODER0_WR_CBASS_MAP(i)                (QOS_ENCODER0_WR + 0x100 + (i) * 4)

#define QOS_DECODER0_RD                             0x45dc0400
#define QOS_DECODER0_RD_NUM_J_CH                    2
#define QOS_DECODER0_RD_NUM_I_CH                    1
#define QOS_DECODER0_RD_CBASS_GRP_MAP1(j)           (QOS_DECODER0_RD + 0x0 + (j) * 8)
#define QOS_DECODER0_RD_CBASS_GRP_MAP2(j)           (QOS_DECODER0_RD + 0x4 + (j) * 8)
#define QOS_DECODER0_RD_CBASS_MAP(i)                (QOS_DECODER0_RD + 0x100 + (i) * 4)

#define QOS_DECODER0_WR                             0x45dc0800
#define QOS_DECODER0_WR_NUM_J_CH                    2
#define QOS_DECODER0_WR_NUM_I_CH                    1
#define QOS_DECODER0_WR_CBASS_GRP_MAP1(j)           (QOS_DECODER0_WR + 0x0 + (j) * 8)
#define QOS_DECODER0_WR_CBASS_GRP_MAP2(j)           (QOS_DECODER0_WR + 0x4 + (j) * 8)
#define QOS_DECODER0_WR_CBASS_MAP(i)                (QOS_DECODER0_WR + 0x100 + (i) * 4)

#define QOS_VPAC0_DATA0                             0x45dc1500
#define QOS_VPAC0_DATA0_NUM_I_CH                    32
#define QOS_VPAC0_DATA0_CBASS_MAP(i)                (QOS_VPAC0_DATA0 + (i) * 4)

#define QOS_DMPAC0_DATA                             0x45dc0100
#define QOS_DMPAC0_DATA_NUM_I_CH                    32
#define QOS_DMPAC0_DATA_CBASS_MAP(i)                (QOS_DMPAC0_DATA + (i) * 4)

#define QOS_ENCODER0_RD                             0x45dc0c00
#define QOS_ENCODER0_RD_NUM_J_CH                    2
#define QOS_ENCODER0_RD_NUM_I_CH                    5
#define QOS_ENCODER0_RD_CBASS_GRP_MAP1(j)           (QOS_ENCODER0_RD + 0x0 + (j) * 8)
#define QOS_ENCODER0_RD_CBASS_GRP_MAP2(j)           (QOS_ENCODER0_RD + 0x4 + (j) * 8)
#define QOS_ENCODER0_RD_CBASS_MAP(i)                (QOS_ENCODER0_RD + 0x100 + (i) * 4)

#define QOS_VPAC0_DATA1                             0x45dc1900
#define QOS_VPAC0_DATA1_NUM_I_CH                    64
#define QOS_VPAC0_DATA1_CBASS_MAP(i)                (QOS_VPAC0_DATA1 + (i) * 4)

#define QOS_VPAC0_LDC0                              0x45dc1c00
#define QOS_VPAC0_LDC0_NUM_J_CH                     2
#define QOS_VPAC0_LDC0_NUM_I_CH                     3
#define QOS_VPAC0_LDC0_CBASS_GRP_MAP1(j)            (QOS_VPAC0_LDC0 + 0x0 + (j) * 8)
#define QOS_VPAC0_LDC0_CBASS_GRP_MAP2(j)            (QOS_VPAC0_LDC0 + 0x4 + (j) * 8)
#define QOS_VPAC0_LDC0_CBASS_MAP(i)                 (QOS_VPAC0_LDC0 + 0x100 + (i) * 4)

#define QOS_DSS0_DMA                                0x45dc2000
#define QOS_DSS0_DMA_NUM_J_CH                       2
#define QOS_DSS0_DMA_NUM_I_CH                       10
#define QOS_DSS0_DMA_CBASS_GRP_MAP1(j)              (QOS_DSS0_DMA + 0x0 + (j) * 8)
#define QOS_DSS0_DMA_CBASS_GRP_MAP2(j)              (QOS_DSS0_DMA + 0x4 + (j) * 8)
#define QOS_DSS0_DMA_CBASS_MAP(i)                   (QOS_DSS0_DMA + 0x100 + (i) * 4)

#define QOS_DSS0_FBDC                               0x45dc2400
#define QOS_DSS0_FBDC_NUM_J_CH                      2
#define QOS_DSS0_FBDC_NUM_I_CH                      10
#define QOS_DSS0_FBDC_CBASS_GRP_MAP1(j)             (QOS_DSS0_FBDC + 0x0 + (j) * 8)
#define QOS_DSS0_FBDC_CBASS_GRP_MAP2(j)             (QOS_DSS0_FBDC + 0x4 + (j) * 8)
#define QOS_DSS0_FBDC_CBASS_MAP(i)                  (QOS_DSS0_FBDC + 0x100 + (i) * 4)

#define QOS_GPU0_M0_RD                              0x45dc5000
#define QOS_GPU0_M0_RD_NUM_J_CH                     2
#define QOS_GPU0_M0_RD_NUM_I_CH                     48
#define QOS_GPU0_M0_RD_CBASS_GRP_MAP1(j)            (QOS_GPU0_M0_RD + 0x0 + (j) * 8)
#define QOS_GPU0_M0_RD_CBASS_GRP_MAP2(j)            (QOS_GPU0_M0_RD + 0x4 + (j) * 8)
#define QOS_GPU0_M0_RD_CBASS_MAP(i)                 (QOS_GPU0_M0_RD + 0x100 + (i) * 4)

#define QOS_GPU0_M0_WR                              0x45dc5800
#define QOS_GPU0_M0_WR_NUM_J_CH                     2
#define QOS_GPU0_M0_WR_NUM_I_CH                     48
#define QOS_GPU0_M0_WR_CBASS_GRP_MAP1(j)            (QOS_GPU0_M0_WR + 0x0 + (j) * 8)
#define QOS_GPU0_M0_WR_CBASS_GRP_MAP2(j)            (QOS_GPU0_M0_WR + 0x4 + (j) * 8)
#define QOS_GPU0_M0_WR_CBASS_MAP(i)                 (QOS_GPU0_M0_WR + 0x100 + (i) * 4)

#define QOS_GPU0_M1_RD                              0x45dc6000
#define QOS_GPU0_M1_RD_NUM_J_CH                     2
#define QOS_GPU0_M1_RD_NUM_I_CH                     48
#define QOS_GPU0_M1_RD_CBASS_GRP_MAP1(j)            (QOS_GPU0_M1_RD + 0x0 + (j) * 8)
#define QOS_GPU0_M1_RD_CBASS_GRP_MAP2(j)            (QOS_GPU0_M1_RD + 0x4 + (j) * 8)
#define QOS_GPU0_M1_RD_CBASS_MAP(i)                 (QOS_GPU0_M1_RD + 0x100 + (i) * 4)

#define QOS_GPU0_M1_WR                              0x45dc6800
#define QOS_GPU0_M1_WR_NUM_J_CH                     2
#define QOS_GPU0_M1_WR_NUM_I_CH                     48
#define QOS_GPU0_M1_WR_CBASS_GRP_MAP1(j)            (QOS_GPU0_M1_WR + 0x0 + (j) * 8)
#define QOS_GPU0_M1_WR_CBASS_GRP_MAP2(j)            (QOS_GPU0_M1_WR + 0x4 + (j) * 8)
#define QOS_GPU0_M1_WR_CBASS_MAP(i)                 (QOS_GPU0_M1_WR + 0x100 + (i) * 4)

#define QOS_MMC0_RD_CBASS_MAP(i)                    (0x45d9a100 + (i) * 4)
#define QOS_MMC0_WR_CBASS_MAP(i)                    (0x45d9a500 + (i) * 4)
#define QOS_MMC1_RD_CBASS_MAP(i)                    (0x45d82100 + (i) * 4)
#define QOS_MMC1_WR_CBASS_MAP(i)                    (0x45d82500 + (i) * 4)

#define QOS_D5520_RD_CBASS_MAP(i)                   (0x45dc0500 + (i) * 4)
#define QOS_D5520_WR_CBASS_MAP(i)                   (0x45dc0900 + (i) * 4)

/* NAVSS North Bridge (NB) */
#define NAVSS0_NBSS_NB0_CFG_MMRS                    0x3702000
#define NAVSS0_NBSS_NB1_CFG_MMRS                    0x3703000
#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP            (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10)
#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP            (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10)

#define QOS_MCU_R5FSS0_CORE0_MEM_RD_ATYPE    (3U)
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_ATYPE    (3U)
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_ORDER_ID (12U)
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_ORDER_ID (12U)
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_PRIORITY (7U)
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_PRIORITY (7U)

#define QOS_MCU_R5FSS0_CORE0_MEM_RD                     0x45d10000
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_J_CH            1
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_I_CH            1
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(j)   (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x0 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(j)   (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x4 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_MAP(i)        (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x100 + (i) * 4)

#define QOS_MCU_R5FSS0_CORE0_MEM_WR                     0x45d10400
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_J_CH            1
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_I_CH            1
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(j)   (QOS_MCU_R5FSS0_CORE0_MEM_WR + 0x0 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(j)   (QOS_MCU_R5FSS0_CORE0_MEM_WR + 0x4 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_MAP(i)        (QOS_MCU_R5FSS0_CORE0_MEM_WR + 0x100 + (i) * 4)

#define QOS_MCU_R5FSS0_CORE1_MEM_RD_ATYPE    (3U)
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_ATYPE    (3U)
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_ORDER_ID (12U)
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_ORDER_ID (12U)
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_PRIORITY (7U)
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_PRIORITY (7U)

#define QOS_MCU_R5FSS0_CORE1_MEM_RD                     0x45d11000
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_NUM_J_CH            1
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_NUM_I_CH            1
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(j)   (QOS_MCU_R5FSS0_CORE1_MEM_RD + 0x0 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(j)   (QOS_MCU_R5FSS0_CORE1_MEM_RD + 0x4 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_MAP(i)        (QOS_MCU_R5FSS0_CORE1_MEM_RD + 0x100 + (i) * 4)

#define QOS_MCU_R5FSS0_CORE1_MEM_WR                     0x45d11400
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_NUM_J_CH            1
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_NUM_I_CH            1
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(j)   (QOS_MCU_R5FSS0_CORE1_MEM_WR + 0x0 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(j)   (QOS_MCU_R5FSS0_CORE1_MEM_WR + 0x4 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_MAP(i)        (QOS_MCU_R5FSS0_CORE1_MEM_WR + 0x100 + (i) * 4)

void setup_navss_nb(void)
{
        /* Map orderid 8-15 to VBUSM.C thread 2 (real-time traffic) */
        CSL_REG32_WR(NAVSS0_NBSS_NB0_CFG_NB_THREADMAP, 2);
        CSL_REG32_WR(NAVSS0_NBSS_NB1_CFG_NB_THREADMAP, 4);
}

void setup_vpac_qos(void)
{
    unsigned int channel, group;

    /* vpac data master 0  */
    for (channel = 0; channel < QOS_VPAC0_DATA0_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_VPAC0_DATA0_CBASS_MAP(channel), (QOS_VPAC0_DATA0_ATYPE << 28));
    }

    /* vpac data master 1  */
    for (channel = 0; channel < QOS_VPAC0_DATA1_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_VPAC0_DATA1_CBASS_MAP(channel), (QOS_VPAC0_DATA1_ATYPE << 28));
    }

    /* vpac ldc0  */
    for (group = 0; group < QOS_VPAC0_LDC0_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_VPAC0_LDC0_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_VPAC0_LDC0_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_VPAC0_LDC0_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_VPAC0_LDC0_CBASS_MAP(channel), (QOS_VPAC0_LDC0_ATYPE << 28) | (QOS_VPAC0_LDC0_PRIORITY << 12) | (QOS_VPAC0_LDC0_ORDER_ID << 4));
    }
}

void setup_dmpac_qos(void)
{
    unsigned int channel;

    /* dmpac data  */
    for (channel = 0; channel < QOS_DMPAC0_DATA_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_DMPAC0_DATA_CBASS_MAP(channel), (QOS_DMPAC0_DATA_ATYPE << 28));
    }
}

void setup_dss_qos(void)
{
    unsigned int channel, group;

    /* two master ports: dma and fbdc */
    /* two groups: SRAM and DDR */
    /* 10 channels: (pipe << 1) | is_second_buffer */

    /* master port 1 (dma) */
    for (group = 0; group < QOS_DSS0_DMA_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_DSS0_DMA_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_DSS0_DMA_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_DSS0_DMA_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_DSS0_DMA_CBASS_MAP(channel), (QOS_DSS0_DMA_ATYPE << 28) | (QOS_DSS0_DMA_PRIORITY << 12) | (QOS_DSS0_DMA_ORDER_ID << 4));
    }

    /* master port 2 (fbdc) */
    for (group = 0; group < QOS_DSS0_FBDC_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_DSS0_FBDC_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_DSS0_FBDC_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_DSS0_FBDC_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_DSS0_FBDC_CBASS_MAP(channel), (QOS_DSS0_FBDC_ATYPE << 28) | (QOS_DSS0_FBDC_PRIORITY << 12) | (QOS_DSS0_FBDC_ORDER_ID << 4));
    }
}

void setup_gpu_qos(void)
{
    unsigned int channel, group;

    /* gpu m0 rd */
    for (group = 0; group < QOS_GPU0_M0_RD_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_GPU0_M0_RD_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_GPU0_M0_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_GPU0_M0_RD_NUM_I_CH; ++channel)
    {
        if(channel == 0)
        {
            CSL_REG32_WR((uintptr_t)QOS_GPU0_M0_RD_CBASS_MAP(channel), (QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4));
        }
        else
        {
            CSL_REG32_WR((uintptr_t)QOS_GPU0_M0_RD_CBASS_MAP(channel), (QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4));
        }
    }

    /* gpu m0 wr */
    for (group = 0; group < QOS_GPU0_M0_WR_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_GPU0_M0_WR_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_GPU0_M0_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_GPU0_M0_WR_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_GPU0_M0_WR_CBASS_MAP(channel), (QOS_GPU0_M0_WR_ATYPE << 28) | (QOS_GPU0_M0_WR_PRIORITY << 12) | (QOS_GPU0_M0_WR_ORDER_ID << 4));
    }

    /* gpu m1 rd */
    for (group = 0; group < QOS_GPU0_M1_RD_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_GPU0_M1_RD_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_GPU0_M1_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_GPU0_M1_RD_NUM_I_CH; ++channel)
    {
        if(channel == 0)
        {
            CSL_REG32_WR((uintptr_t)QOS_GPU0_M1_RD_CBASS_MAP(channel), (QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4));
        }
        else
        {
            CSL_REG32_WR((uintptr_t)QOS_GPU0_M1_RD_CBASS_MAP(channel), (QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4));
        }
    }

    /* gpu m1 wr */
    for (group = 0; group < QOS_GPU0_M1_WR_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_GPU0_M1_WR_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_GPU0_M1_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_GPU0_M1_WR_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_GPU0_M1_WR_CBASS_MAP(channel), (QOS_GPU0_M1_WR_ATYPE << 28) | (QOS_GPU0_M1_WR_PRIORITY << 12) | (QOS_GPU0_M1_WR_ORDER_ID << 4));
    }
}

void setup_encoder_qos(void)
{
    unsigned int channel, group;

    /* encoder rd */
    for (group = 0; group < QOS_ENCODER0_RD_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_ENCODER0_RD_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_ENCODER0_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_ENCODER0_RD_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_ENCODER0_RD_CBASS_MAP(channel), (QOS_ENCODER0_RD_ATYPE << 28) | (QOS_ENCODER0_RD_PRIORITY << 12) | (QOS_ENCODER0_RD_ORDER_ID << 4));
    }

    /* encoder wr */
    for (group = 0; group < QOS_ENCODER0_WR_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_ENCODER0_WR_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_ENCODER0_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_ENCODER0_WR_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_ENCODER0_WR_CBASS_MAP(channel), (QOS_ENCODER0_WR_ATYPE << 28) | (QOS_ENCODER0_WR_PRIORITY << 12) | (QOS_ENCODER0_WR_ORDER_ID << 4));
    }
}

void setup_decoder_qos(void)
{
    unsigned int channel, group;

    /* decoder rd */
    for (group = 0; group < QOS_DECODER0_RD_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_DECODER0_RD_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_DECODER0_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_DECODER0_RD_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_DECODER0_RD_CBASS_MAP(channel), (QOS_DECODER0_RD_ATYPE << 28) | (QOS_DECODER0_RD_PRIORITY << 12) | (QOS_DECODER0_RD_ORDER_ID << 4));
    }

    /* decoder wr */
    for (group = 0; group < QOS_DECODER0_WR_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_DECODER0_WR_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_DECODER0_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_DECODER0_WR_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_DECODER0_WR_CBASS_MAP(channel), (QOS_DECODER0_WR_ATYPE << 28) | (QOS_DECODER0_WR_PRIORITY << 12) | (QOS_DECODER0_WR_ORDER_ID << 4));
    }
}

void setup_main_r5f_qos(void)
{
    unsigned int channel, group;

    /* R5FSS0 core0 - read */
    for (group = 0; group < QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(channel), (QOS_R5FSS0_CORE0_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4));
    }

    /* R5FSS0 core0 - write */
    for (group = 0; group < QOS_R5FSS0_CORE0_MEM_WR_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_WR_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_MAP(channel), (QOS_R5FSS0_CORE0_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4));
    }

    /* R5FSS0 core1 - read */
    for (group = 0; group < QOS_R5FSS0_CORE1_MEM_RD_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_RD_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_MAP(channel), (QOS_R5FSS0_CORE1_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4));
    }

    /* R5FSS0 core1 - write */
    for (group = 0; group < QOS_R5FSS0_CORE1_MEM_WR_NUM_J_CH; ++group)
    {
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_WR_NUM_I_CH; ++channel)
    {
        CSL_REG32_WR((uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(channel), (QOS_R5FSS0_CORE1_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE1_MEM_RD_ORDER_ID << 4));
    }

}

void setup_mcu_r5f_qos(void)
{
    unsigned int channel, group;

    /* MCU_R5FSS0 core0 - read */
    for (group = 0; group < QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_J_CH; ++group) {
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_I_CH; ++channel) {
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_MAP(channel), (QOS_MCU_R5FSS0_CORE0_MEM_RD_ATYPE << 28) | (QOS_MCU_R5FSS0_CORE0_MEM_RD_PRIORITY << 12) | (QOS_MCU_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4));
    }

    /* MCU_R5FSS0 core0 - write */
    for (group = 0; group < QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_J_CH; ++group) {
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_I_CH; ++channel) {
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_MAP(channel), (QOS_MCU_R5FSS0_CORE0_MEM_WR_ATYPE << 28) | (QOS_MCU_R5FSS0_CORE0_MEM_WR_PRIORITY << 12) | (QOS_MCU_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4));
    }

    /* MCU_R5FSS0 core1 - read */
    for (group = 0; group < QOS_MCU_R5FSS0_CORE1_MEM_RD_NUM_J_CH; ++group) {
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_MCU_R5FSS0_CORE1_MEM_RD_NUM_I_CH; ++channel) {
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_MAP(channel), (QOS_MCU_R5FSS0_CORE1_MEM_RD_ATYPE << 28) | (QOS_MCU_R5FSS0_CORE1_MEM_RD_PRIORITY << 12) | (QOS_MCU_R5FSS0_CORE1_MEM_RD_ORDER_ID << 4));
    }

    /* MCU_R5FSS0 core1 - write */
    for (group = 0; group < QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_J_CH; ++group) {
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
    }

    for (channel = 0; channel < QOS_MCU_R5FSS0_CORE1_MEM_WR_NUM_I_CH; ++channel) {
        CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_MAP(channel), (QOS_MCU_R5FSS0_CORE1_MEM_WR_ATYPE << 28) | (QOS_MCU_R5FSS0_CORE1_MEM_WR_PRIORITY << 12) | (QOS_MCU_R5FSS0_CORE1_MEM_RD_ORDER_ID << 4));
    }

}
void setup_main_r5f1_qos(void)

{

    unsigned int channel, group;


    /* R5FSS1 core0 - read */

    for (group = 0; group < QOS_R5FSS1_CORE0_MEM_RD_NUM_J_CH; ++group)
    {
        CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
    }


    for (channel = 0; channel < QOS_R5FSS1_CORE0_MEM_RD_NUM_I_CH; ++channel)
    {
	UART_printf("**************\r\nDebug:func:%s,line=%d\r\n***************, RD = %x\r\n",__FUNCTION__,__LINE__,CSL_REG32_RD((uintptr_t)QOS_R5FSS1_CORE0_MEM_RD_CBASS_MAP(channel)));
       CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_RD_CBASS_MAP(channel), (QOS_R5FSS0_CORE0_MEM_RD_ATYPE << 28) | (QOS_R5FSS1_CORE0_MEM_RD_PRIORITY << 12) | (QOS_R5FSS1_CORE0_MEM_RD_ORDER_ID << 4));
	UART_printf("**************\r\nDebug:func:%s,line=%d\r\n***************, RD = %x\r\n",__FUNCTION__,__LINE__,CSL_REG32_RD((uintptr_t)QOS_R5FSS1_CORE0_MEM_RD_CBASS_MAP(channel)));
    }



    /* R5FSS1 core0 - write */

    for (group = 0; group < QOS_R5FSS1_CORE0_MEM_WR_NUM_J_CH; ++group)
    {
        CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP1(group), 0x76543210);
        CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
    }


    for (channel = 0; channel < QOS_R5FSS1_CORE0_MEM_WR_NUM_I_CH; ++channel)
    {
	UART_printf("**************\r\nDebug:func:%s,line=%d\r\n***************, RD = %x\r\n",__FUNCTION__,__LINE__,CSL_REG32_RD((uintptr_t)QOS_R5FSS1_CORE0_MEM_WR_CBASS_MAP(channel)));
        CSL_REG32_WR(QOS_R5FSS1_CORE0_MEM_WR_CBASS_MAP(channel), (QOS_R5FSS0_CORE0_MEM_WR_ATYPE << 28) | (QOS_R5FSS1_CORE0_MEM_WR_PRIORITY << 12) | (QOS_R5FSS1_CORE0_MEM_RD_ORDER_ID << 4));
	UART_printf("**************\r\nDebug:func:%s,line=%d\r\n***************, RD = %x\r\n",__FUNCTION__,__LINE__,CSL_REG32_RD((uintptr_t)QOS_R5FSS1_CORE0_MEM_WR_CBASS_MAP(channel)));
    }

}
static void J721S2_SetupQoS()
{
    setup_navss_nb();
    /* Workaround to unblock PDK-8359 .
     * setup_main_r5f_qos() results in crashing the UDMA DRU examples on
     * mcu2_0(with SBL uart boot mode) during CSL_REG64_WR(&pRegs->DRUQueues.CFG[queueId], regVal);
     * Hence commenting out the following. */
    setup_main_r5f_qos();
    setup_mcu_r5f_qos();
    setup_vpac_qos();
    setup_dmpac_qos();
    setup_dss_qos();
    /* setup_gpu_qos(); */
    setup_encoder_qos();
    /* setup_main_r5f1_qos(); */
}
#endif

/* This function is to be called from other apps (e.g., mcusw boot app) to set QoS settings */
void SBL_SetQoS()
{
#if defined(SOC_J721S2)
    J721S2_SetupQoS();
#endif
}

0 Brijesh Jadav over 1 year ago in reply to Gaston yan

TI__Guru**** 477995 points

Hi Gaston yan,

The changes look fine to me.

Any specific reason you want to change priority for main domain R5F also? Can you try commenting out call to setup_main_r5f_qos and see if it helps?

Regards,

Brijesh

+1 Gaston yan over 1 year ago in reply to Brijesh Jadav

Intellectual 545 points

Hi Brijesh:

We didn't verify it properly at the beginning, but now we find that my previous program is effective. This issue can be closed.

0 Brijesh Jadav over 1 year ago in reply to Gaston yan

TI__Guru**** 477995 points

Thanks Gaston Yan, closing this ticket.

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TDA4VL-Q1: MCU DDR access priority