Hi,
We are using a Xilinx Spartan 6 FPGA PCIe to interface to our AM389x CPU.
From the datasheet of the Spartan 6 FPGA integrated Endpoint Block, it says:
1) PCIe Base Specification Compliance v1.1
2) 2.5Gb/s, x1 lane
3) user interface width: 32
4) End points only
Then from the datasheet at the AM389x (cpu):
1) PCIe port x2 lanes GEN2 compliance interface, 5Gp/s or 2.5Gp/s
2) Root complex or end point
My questions:
1) So can I confirm that the AM389x can support the Xilinx Spartan6 FPGA PCIe v1.1 and I can safely connect the signals ie Tx (AM389x) to Rx (fpga) directly just by adding a capacitors?
2) If the AM389x connects to a PCIe v1.1 device, will they auto-negotiate the speed to 2.5Gp/s or must we initialise any registers at the AM389x to let it run 2.5Gp/s?
3) How do we configure the AM389x as root complex?
4) If we are not using one of the lanes of the PCIe at AM389x, can we just float the TX/RX/CLOCK signals? or the RX has to be tied to Gnd while the other signals can be floated?
Thanks,
Eng Hong
