TMS320C6655: TMS320C6655/7 - DDR3 Calculation excel document

this what i filled as for:

1. DDR3 (4Gb, 1600Mbps) which connected to DSP TMS320C6655 or 6657 (Single / Dual Core).

2. CLK Generator supply to DSP: 66.66MHz 

3. Not using ECC

4. Board FR4

5. mean values of differential signals (i.e. CK_P = 0.659 , CK_N = 0.650 --> CK filled in table = 0.654)

or should i fill it like below (C665x section):

Daniel,

Daniel Hoasov Cohen said:

1. I have excel file: "DDR3 PHY Calc v11" (from 03/10/2014). There is latest version of this file in order to calculate the Registers Values?

The excel sheet given in this FAQ is the latest one.

[FAQ] TMS320C6657: How to calculate the "DDR3 Interface – Registers" for Keystone I devices and Test/Debug on Keystone I EVM. - Processors forum - Processors - TI E2E support forums

Daniel Hoasov Cohen said:

2. Also, I would like to know how to fill the table correctly if im using single DDR3 (4Gb, 1600Mbps) which connected to DSP TMS320C6655 or 6657 (Single / Dual Core).

Let me look at it and get back.

Daniel Hoasov Cohen said:

The table refer to DQS0 / DQS1… (DDR EMIF Data Strobe) but they are differential signals, its should be DQS0_P, DQS0_N… (positive and negative)
Also, for CK (clock) its should be CK and CK_N (positive and negative).
If I fill in only DQS0, CK_0 and DQS1 all other columns are empty (0), as result, the Hex Values are 0 too.

Looping in Kyle to comment on this question.

Regards

Shankari G

Hi Shankari,

The link below does not seem to download the file when I try to download it

http://www.ti.com/lit/zip/sprabl2 

Daniel,

Even, initally I faced this problem. But here, though it does not seem to be, it will be in your Download folder. 

Check again.

Regards

Shankari G

thank you, waiting for kcastille comment regarding the questions below:

1.Also, I would like to know how to fill the table correctly if im using single DDR3 (4Gb, 1600Mbps) which connected to DSP TMS320C6655 or 6657 (Single / Dual Core).

The table refer to DQS0 / DQS1… (DDR EMIF Data Strobe) but they are differential signals, its should be DQS0_P, DQS0_N… (positive and negative)
Also, for CK (clock) its should be CK and CK_N (positive and negative).
If I fill in only DQS0, CK_0 and DQS1 all other columns are empty (0), as result, the Hex Values are 0 too.

2. this what i filled as for:

a. DDR3 (4Gb, 1600Mbps) which connected to DSP TMS320C6655 or 6657 (Single / Dual Core).

b. CLK Generator supply to DSP: 66.66MHz 

c. Not using ECC

d. Board FR4

e. mean values of differential signals (i.e. CK_P = 0.659 , CK_N = 0.650 --> CK filled in table = 0.654)

or should i fill it like below (C665x section):

Daniel,

Please post/attach it in the form of Excel format.

Likewise the schematics also, attach as pdf or some doc format.

When I maximize the pics, it loses it clarity.

--

Please note, I will be out of office from 6th to 9th of August.

After you attach them in Excel format, let me review the register values and get back to you.

Regards

Shankari G

Dear Shankari G,

Please find attached:

- PDF file of the specific page from the schematics design

- Excel file of TI table 

- 3 pictures of Net length from the layout design

DSP_6655_57_to_Single_DDR3_4Gb.pdf

DSP_6655_57_to_Single_DDR3_4Gb_TI_Table.xlsx

Hello Daniel,

Our expert, Sankari, taking care of this thread, is out of the office from the 6th to the 9th of August; hence, please expect a delay in responses.

Thanks.

Hi Praveen Rao,

Thanks for the reply,

ok ill wait for Sankari Shankari G and Kyle kcastille reply

Daniel,

As per the Data manual of C6655/C6657, the maximum data rate is 1333 MT/s

                   -----> page no:7 https://www.ti.com/lit/ds/symlink/tms320c6655.pdf

In your design, you selected "DDR3 (4Gb, 1600Mbps )".

Please note,  while calculating the DDR3 register values using the Excel sheet, please select the speed as 1333.

Sample DDR3 register Excel sheet : - 4682.DDR3 Register Calc v4.xlsx

Please post your DDR3 register Excel sheet.

For example:- 

--

Data sheet of C6655 / C6657

– 32-Bit DDR3 Interface

     – DDR3-1333

      – 4GB of Addressable Memory Space

---

---

Schematics of TI-C6657-EVM with DDR3 memory interface - TMDXEVM6657Lx_EVM_SCH_16_00132_02.pdf

Memories - Micron T41J128M16HA-125 and MT41J256M16RE-125

Sample DDR3 PHY calc sheet for comparing with yours.

4503.DDR3 PHY Calc v11.xlsx

Regards

Shankari G

Hi Shankari,

Please find attached:

- PDF file of the specific page from the schematics design

- Excel file of TI table

- 3 pictures of Net length from the layout design

DSP_6655_57_to_Single_DDR3_4Gb.pdf

Daniel_DDR3 PHY Calc v11.xlsx

Questions for file Daniel_DDR3 PHY Calc v11.xlsx:

1. We decide to use 4Gb, 1866Mbps because of cost effective reasons, As we already know (as you described it in previous comment) the DSP can use Max of 1333Mbps from DDR, so the DDR will not work at full operating frequency of 1866, but 1333 is under compatibility of the DDR.

2. Other board parameters - CLK Generator supply to DSP: 66.66MHz, Not using ECC, Board FR4.

3. The table refer to DQS0 / DQS1… (DDR EMIF Data Strobe) but they are differential signals, its should be DQS0_P, DQS0_N… (positive and negative). Also, for CK (clock) its should be CK and CK_N (positive and negative).

If I fill in only DQS0, CK_0 and DQS1 all other columns are empty (0), as result, the Hex Values are 0 too, its ok to keep it like that?

4. I filled in the mean values of differential signals because of section 2 above (i.e. CK_P = 0.659 , CK_N = 0.650 --> CK filled in table = 0.654)

Questions for file 4503.DDR3 PHY Calc v11.xlsx (you sent me in previous comment):

DDR P/N: NT5CC256M16ER-EK

DDR MFG: Nanya

DDR Datasheet: Nanya-NT5CC256M16ER-EK.PDF

1. I didn't understand if should I use 1888 Mbps paraments of the DDR from the datasheet (i.e CL-TRCD-TRP paraments) or I need to use 1333 Mbps (different P/N that I current use) parameters to fit DSP DDR max compatibility?

2. I don't find my DDR3 under "Device and speed grade" list in the document, how to define new one if i selected "User defined"? i can't change the parameters values under the list its locked.

Thank you for your assistance.

Daniel Hoasov Cohen said:

1. We decide to use 4Gb, 1866Mbps because of cost effective reasons, As we already know (as you described it in previous comment) the DSP can use Max of 1333Mbps from DDR, so the DDR will not work at full operating frequency of 1866, but 1333 is under compatibility of the DDR.

Yes. That's my point. We have to make sure that we set the operating frequency of the memory as 1333 and not beyond that.

For example, the other keystone devices like C6678, will support upto 1600 MT/s but C665x can support only upto 1333.

Daniel Hoasov Cohen said:

2. Other board parameters - CLK Generator supply to DSP: 66.66MHz, Not using ECC, Board FR4.

3. The table refer to DQS0 / DQS1… (DDR EMIF Data Strobe) but they are differential signals, its should be DQS0_P, DQS0_N… (positive and negative). Also, for CK (clock) its should be CK and CK_N (positive and negative).

If I fill in only DQS0, CK_0 and DQS1 all other columns are empty (0), as result, the Hex Values are 0 too, its ok to keep it like that?

I saw those values as Zero in your sheet. Let Kyle comment on that.

-----

In my previous post, I have attached "the DDR3 register- Excel sheet". 

Yes, you have to select the option as " user defined".  

===========

IMPORTANT:- 

===========

Question 1:-

Daniel Hoasov Cohen said:

1. I didn't understand if should I use 1888 Mbps paraments of the DDR from the datasheet (i.e CL-TRCD-TRP paraments) or I need to use 1333 Mbps (different P/N that I current use) parameters to fit DSP DDR max compatibility?

Yes, you have to select the CL-TRCD-TRP parameters to fit the DSP DDR max speed ----> i.e 1333.

I looked into the "DDR Datasheet: Nanya-NT5CC256M16ER-EK.PDF"

BUT HERE, as per your memory Datasheet, there are only three speeds are available in the part you have chosen for your design ???

Speed Grade (CL-TRCD-TRP)

      - 2133 Mbps / 14-14-14

      - 1866 Mbps / 13-13-13

      - 1600 Mbps / 11-11-11

In the rest of the data sheet, they have given that the lower frequencies are also supported.

You better enquire the Nanya on how to set the parameters - "CL-TRCD-TRP" for 1333.

----

Daniel Hoasov Cohen said:

2. I don't find my DDR3 under "Device and speed grade" list in the document, how to define new one if i selected "User defined"? i can't change the parameters values under the list its locked.

Question 2:-

You can fill only the "yellow-shaded" cells. It will automatically fill the register values. Focus only on yellow cells.

In the Excel sheet, go to the "FIFTH sheet" -- Device and speed grade," Data sheet" ----> column "AG" and fill the details according to the data given in your DDR3 memory-Datasheet ( Here, your datasheet is  Nanya-NT5CC256M16ER-EK.PDF"

I hope this helps !

Regards

Shankari G

Shankari G said:

I saw those values as Zero in your sheet. Let Kyle comment on that.

Ok i'll wait for Kyle comment for DDR3 PHY Calc excel

Shankari G said:

You better enquire the Nanya on how to set the parameters - "CL-TRCD-TRP" for 1333.

asked, soon as i have the response i post it here with updated DDR3 Register calc excel

Daniel,

Sure. I will wait for your reply.

Regards

Shankari G

Hello Daniel,

Are you only interfacing to 16-b of external DDR memory?

In any case, you're correct that each cell represents the length of the DQSxP and DQSxN pair.  Considering this is setting the "initial" value for the leveling operation, it doesn't have to be perfect rather it needs to be set to a valid value within the range such that the leveling algo can find the center/optimal value.

You should also fill in the CK1 value (it can match the CK0 value).

It may also be a good idea to fill in for both the DQS[1:0] as well as DQS[5:4].  

Regards,

Kyle

Hi Kyle,

Thank you for your comment, 

kcastille said:

Are you only interfacing to 16-b of external DDR memory?

Yes, I'm using only single 16b DDR3 (256Mx16).

kcastille said:

You should also fill in the CK1 value (it can match the CK0 value).

I filled CK1 value as the same as CK0. (Although I don't really have CK1 actually connection from Gauss DSP to any DDR).

I did the same for C665x DQS[2:3] (same value as C665x DQS[0:1]).

• I wonder what should i fill in / or leave empty the other 0.000 values? (DQS0, CK_0, DQS1, CK_1, DQS2, CK_2, DQS3, CK_3, C665x CK_2, C665x CK_3, DQS_ECC, CK_ECC)

Please find attached updated, please let me know if I missed something:

3835.Daniel_DDR3 PHY Calc v11.xlsx

6558.DSP_6655_57_to_Single_DDR3_4Gb.pdf

Hi Kyle (kcastille),

kcastille said:

Daniel,

Copy/pasting into the other unused cells can't hurt, and I would recommend it.

The trick will be having software enable/configure only the byte lanes that are physically populated.  Have you run on hardware yet?

Thanks,
Kyle

Please find attached,

i copy/pasting into other unused cells (actually im using only only C665x DQS0, C665x CK_0 & C665x DQS1).

please let me know if its ok now according to the PDF and pictures attached at my last comment.

NT5CC256M16ER-EK_DDR3 PHY Calc v11.xlsx

No, I don't have HW yet

Daniel,

May be, I guess, reviewing all your values are beyond the scope of Forum support.

May be once you receive the hardware, you can try it out as Kyle suggested.

Regards

Shankari G

Shankari G said:

May be once you receive the hardware

Hi,

What test should I run in order to check if these parameters (NT5CC256M16ER-EK_DDR3 PHY Calc v11.xlsx) ok or need to change