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PROCESSOR-SDK-AM62X: When making custome board, wanting full DDR training application

Part Number: PROCESSOR-SDK-AM62X
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Im used to other vendors offering a small application that can be loaded into SRAM and will generate a completely optimized eye diagram centering and selection of drive strengths and terminations that are best for this HW platform. the results of this are automatically converted to register values that can be compiled into U-Boot afterwards to make new board bring up simple.
For TI i keep seeing a config tool online that is static and I don't understand how this can ever be optimized for HW or where this process is being automated in any way.
Am i missing something or is this a completely missing tool from TI?
I'd expect to be able to push something into sram using DFU mode over USB that will provide serial output of this optimized training result.

another way of asking similar question is where is the slick optimized method from TI to get optimized DDR setup for a custom board outside of basic memory type and organization that sysconfig is doing?

  • Hi Jesse, what we have is not quite that automated. 

    The DDR config tool (for AM62x it is here:  https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM62x) facilitates generating the initial configuration file that you would build into the SDK for your board.  You would input some basic system configuration based on the memory you choose.  It also has timing inputs (gather from the DDR datasheet) and IO settings (termination, drive strength settings) that are typically derived from a board simulation.  This should get you up and running initially.

    To determine optimized settings, we have the DDR margin tool https://www.ti.com/tool/download/DDR-MARGIN-FW/1.8.0 which performs a 2D sweep of VREF and delay values to generate a virtual data eye and associated margin timing.  This will help you determine marginality on the settings from the config tool.

    A lot of our customers use board simulations to determine optimal drive and termination settings.  We are striving to make the process more automated, much like you describe, but that is not available at this time.

    There are also some hardware app notes to achieve a successful design:

    https://www.ti.com/lit/pdf/sprad06

    https://www.ti.com/lit/pdf/spraar7

    Regards,

    James

  • this is getting closer to what i was thinking. a basic tuning estimate from the board design but followed up with that DDR margin tool sounds like what i was looking for. well at least at a first pass level of verification on real HW.
    let me investigate this in more detail as it might be enough.

    but yes a SRAM based simple shell app that can do full sweep of drive strength options and delays. even if its staged, meaning it takes multiple runs to test out various approaches that you have to select. this would be the sort of one stop shop for board bring up and getting maximum margin / verify that you have margin tool.

    we are working right now on the layout of a new platform with AM62X and some decisions that ultimately lead to needing a way to verify margin on real HW when we get it. so at the least that tool you mention may get us that much.
    ill play around with this on the EVM. 
    Thanks!

  • ok, closing the thread, but feel free to start another if you have further questions.

    Rgards,

    James