TDA4VL-Q1: RGMII TX Data to Clock skew tunning

Hi,

Kevin Kuo said:

Therefore, I would like to know is there any register used to adjust the CLK and DATA timing?

RGMII Tx side, we don't have granular control of clock skew for adjusting to different delay.

We have register to enable delay on RGMII Tx using RGMII-ID from CTRLMMR ENET Control register, which enabled internal delay as per standard.

Kevin Kuo said:

As you can see, the time difference is 9.974ns now, and the specification we would like to achieve is between 1 to 2.6ns.

Check from schematic how delay it is contributing, as MAC side Tx can provide a standard delay ~2nsec not more than that.

Kevin Kuo said:

Please help reply whether the register does exist or not?

Yes, Register exists Please refer to CTRL MMR ENET Control register.

Also, refer to FAQ for more details. 

Best Regards,
Sudheer

Dear Sudheer,

Does the delay may be contributed by the length mismatch between CLK and Data?

Could you please help provide the RGMII layout guide and topology for TDA4AL?

We want to check whether there is any problem with our layout.

Many thanks.

Kevin Kuo

Hi,

Kevin Kuo said:

Does the delay may be contributed by the length mismatch between CLK and Data?

Probably. Please refer to TI EVM schematics as reference.

Please refer to below Appnote for the checklist.
https://www.ti.com/lit/an/sprad91b/sprad91b.pdf?ts=1723113528096&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTDA4VL-Q1

Also, refer to TI EVM schematics and compare with yours.
https://www.ti.com/product/TDA4VL-Q1#design-development

Best Regards,
Sudheer

Dear Sudheer,

There is no RGMII layout guide in the link you provided.

And the checklist does not include any RGMII checkpoint.

Is there trace length limitation or data to clk trace tuning guide?

Many thanks.

Kevin Kuo

Hi,

Kevin Kuo said:

Is there trace length limitation or data to clk trace tuning guide?

Have you referred to TI EVM schematics? EVM has RGMII schematics. Please refer to below once, EVM Page has schematic design files for reference.

Doredla Sudheer Kumar said:

Also, refer to TI EVM schematics and compare with yours.
https://www.ti.com/product/TDA4VL-Q1#design-development

Can you please create new thread and share schematics, our H/W team will review and provide feedback.

Best Regards,
Sudheer