TDA4VM: UART FIFO

Hi Manisha,

Can you confirm if the FIFO is empty before writing the first byte?

You are saying that you see the TX_FIFO is immediately full after writing only one byte?
Thanks,

Neehar

Hello Neehar,
FIFO is empty before writing the first byte. I checked TX_SR_E and TX_FIFO_E  in the UART_LSR_UART register. 
TX_FIFO is full after writing only one byte.

I have found that Transmit holding register (UART_THR) is empty for the first transmission of the data in  a loop. For other iterations in a loop Transmit holding register (UART_THR) is never empty. If I wait until this register is empty then I am able to send all the data I wanted. Can you please tell me also what is the time required to transmit the data from Transmit holding register (UART_THR) to FIFO(time required for the UART_THR register to become empty). 

Thanks
Manisha N G

Hi Manisha,

Have you set the FIFO trigger level?

We are unable to tell the time required to transmit the data from UART_THR to the 64-byte transmit FIFO but it can be tested.
Thanks,

Neehar

Hello Neehar,
I am working on Pooling mode.There are no interrupts set and DMA mode is disabled. Only 2 bytes of data are sent after that FIFO is full. What can be the reason for it.
Initialization of the function includes:

• Reset the module by clearing the bit SOFTRESET of SYSC register
• Wait till the reset is done
• Disable the uART BY SETTING mode_select to 7
• Disable all the interrupts
• Disable the interrupts of FIFO from IER2 register
• Enable the FIFO
• CLears fifo by TX_FIFO_CLEAR 
• Disable DMA mode
• Enable DIV_EN of LCR register
• Configure MODE_SELECT based on baud rate
• Configure CLOCK_LSB AND CLOCK_MSB
• Configure CHAR_LENGTH, NB_STOP, PARITY_EN, BREAK_EN

Please let me know if I need to change anything?

Hi Manisha,

Let me look into this further and get back to you.

Thanks,

Neehar

Hi Manisha,
Sorry for the delay in response. Is this issue still open?
Thanks,

Neehar

Hi Manisha,

Closing this due to inactivity.

Thanks,

Neehar