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Cache write-through on OMAP-l137?

Other Parts Discussed in Thread: OMAP-L137, SYSBIOS

Is there a way to enable a cache write-through mode on OMAP-l137.  All the examples I see seem to be of the all-or-nothing, cache-or-no-cache method.   The reference material for OMAP-L137 mentions a write-through mode, but the dspbios configuration documentation doesn't seem to indicate how to do this.

Ideas?

Thanks,
Chris 

  • Which version of BIOS are you using?

    If you are using SYSBIOS 6.x, see the CDOC for the module ti/sysbios/family/arm/arm9/Mmu.xdc.  There's a short description and sample code.

    In short summary, when you setup the MMU for a particular address range you can set the attributes for that range.  If you set cacheable to 'true' and bufferable to 'false' for that address range the cache will operate as a write-through cache.

    Judah

  • Judah,

    I'm using DSPBIOS 5.41.00.06.  Is there an example for that system?

    Thanks,
    Chris 

  • Chris,

    Are you talking for the ARM or DSP?  I assumed ARM because only ARM supports a write-through cache.  However, BIOS 5.x does not support ARM.

    If you were on BIOS 6.x the best place would be to check out the CDOC.  There is no example for setting up the cache this way.

    Judah

  • I was talking DSP, actually.  I thought I saw something that said the DSP supported write-back cache, but could have easily been mistaken.

    On a side note: you say that BIOS 5.x does not support ARM.  I think I'm wrestling with some cache coherency issues between the ARM and DSP.  Essentially I set up a data buffer on the ARM, and set a control word.  The DSP checks this control word periodically and when it is set to a certain value will take the data and process it.  It then is supposed to reset that control word to let the ARM know all is well.

    I know I can use the calls HAL_cacheInv and HAL_cacheWb on the DSP side, and I've seen a lot of posts telling me I should be using BCACHE.  This all should work fine on the DSP side -- but what do I call on the ARM?

    Chris

     

  • I should probably mention the memory that I'm sharing is in L3 Shared Ram.  I've tried turning off the cache in the tconf file on the DSP side and it didn't seem to help

    Thanks,
    Chris 

  • Chris,

    Are you running Linux on the ARM?  BIOS 5.x doesn't support ARM so you couldn't possible be running BIOS on the ARM?

    You are correct in that the DSP supports a write-back cache, but not write-through cache.  You can use the BCACHE APIs to force the Cached lines to be written out.  Something like:

        BCACHE_wbInv(Ptr blockPtr, size_t byteCnt, Bool wait) or BCACHE_wb(Ptr blockPtr, size_t byteCnt, Bool wait)

    Also, if you are sharing some memory between ARM and DSP you need to make sure this memory is aligned to the bigger cache line size.  Most likley this is the DSP's L2 Cache Line size which is 128 bytes.

    Judah

  • Judah,

    Yeah, I'm running Linux.  Sorry I wasn't clear on that.  To be specific I'm running Timesys Linux on the L137 EVM.  If I understand the documentation I've read (no concise examples, just pulling things from various places) I need to use BCACHE on both the ARM and the DSP to flush the caches.

    I'm having trouble getting that to work, but I think it's a configuration thing.  I just found out that the errors I was generating inserting #include<bcache.h> in to my ARM side code may have to do with the placement of the bios/packages/ti/bios/include directory before the dsplink directories in my compile line.

    Now I'm having trouble finding the methods in the objects... looks like I may not be including the right libraries.

    It would be nice to have an example similar to what I want to do (If what I want to do is valid in the first place.)

    Thanks,

    Chris