AM62A7-Q1: AM62A opp low

Hello, 

Yes, OPP Low is possible on AM62A. Please see the datasheet for AM62A, Section 7.5 Operating Performance Points: https://www.ti.com/lit/ds/symlink/am62a7.pdf

Which module section do you want to change to OPP Low? Is it Main CBASS?

Best Regards,

Anshu

Yes we are developing on custom board now.

We are looking into opp low for power reduction.

How to do cbass low

Regards

Kim

Hello,

PLL0, HSDIV0 is the clock source for the Main CBASS. This means the HSDIV divides the PLL Clock speed to meet the required input clock requirements.

By default, PLL0 is 2000MHz. The HSDIV0 divides the PLL Clock by 4 to make 500MHz (2000MHz/4 = 500MHz). To implement OPP Low for CBASS, you'll have to divide by 8 to make 250MHz as stated in the datasheet. (2000MHz/8 = 250MHz).

You can use the Clock Tree Tool for AM62A to see what register configuration is needed: https://www.ti.com/tool/CLOCKTREETOOL

Or you'll have to directly modify the DM Firmware.

Best Regards,

Anshu

Hi,

Thanks to this, I was able to change the frequency.

Where can I set MCU R5 SYSYCLK and DM R5 CLK as shown in the picture below?

When I proceed with the sysconfig tool, it looks like below. Are they using the same clock?

I'm confused because the values ​​are different.

Regards,

Kim