TDA4VH-Q1: CSI initialisation is failing.

Wojciech Godek

Part Number: TDA4VH-Q1

Tool/software:

Hello,

I tried to setup csi channel according to example (SOC_J784s4 MCU3_0)
pdk_j784s4_09_02_00_30/packages/ti/drv/csirx/examples/csirx_capture_test

1. UdmaInitPrms_init(UDMA_INST_ID_BCDMA_0)
got follwoing error with VINTR =0:
[UDMA] [Error] VINTR alloc failed!!!
[UDMA] [Error] Event 5 config failed!!
[UDMA] [Error] Global master event register failed!!!

2. When UdmaInitPrms_init(UDMA_INST_ID_MAIN_0)
got a problem with chHandle->cqRing =NULL (is not allocated):
[UDMA] [Info] chHandle->fqRing A5576C80, instT 0 ret 0

Could you please provide a hint why the startup config is failing?

Best Regards

Wojciech Godek

over 1 year ago

0 Stefan_Haas over 1 year ago

TI__Mastermind 25212 points

Hello Wojciech,

are you working with your custom board or the TI EVM (with fusion board)?

What is connected to the CSI2RX port?

Are you using this description here: 4.20. CSIRX — Platform Development Kit (PDK) - J784S4 User Guide (ti.com) ?

Thanks, Stefan

0 Wojciech Godek over 1 year ago in reply to Stefan_Haas

Prodigy 40 points

Hello Stefan,

I am working with custom board. CSI is connected to deserializer but at the moment the CSI driver initialization is failing.

Example app from pdk_j784s4_09_02_00_30/packages/ti/drv/csirx/examples/csirx_capture_test

What I can see:

1. configuration in udma_rmcfg.c/gVintInstShare[] is different for MCU3_0 and MCU2_0. For 2_0 no issue with VINTR.

2. chHandle->fqRing (chHandle->cqRing =NULL) is not allocated.

Wojciech

0 Brijesh Jadav over 1 year ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Hello Wojciech,

Any specific reason for checking CSIRX from mcu3_0? This is because by default, in SDK, CSIRX is used from mcu2_0 and so all the required resources are allocated to mcu2_0. Can you try using it from mcu2_0?

Regards,

Brijesh

0 Wojciech Godek over 1 year ago in reply to Brijesh Jadav

Prodigy 40 points

With MCU2_0 CSI is initilaised.

Other question is about I2C. We use I2C1(AE34/AJ32),I2C2(AC32/AC37),I2C3(AF38/AA32),I2C4(AG38,AK34).
I2C is not working at the moment.
What shall be the corrct settings:
- pinmuux
- I2c driver (BASE_ADDR, any other)?

Wojciech

0 Brijesh Jadav over 1 year ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Hi,

Is I2C instance that you are using on mcu2_0 disabled from Linux? If not, can you please try with disabling it from Linux dtb files?

Once disabled, you would need to set pinmux for the instance from mcu2_0, power it on and then can start using this instances from mcu2_0.

Regards,

Brijesh

0 Wojciech Godek over 1 year ago in reply to Brijesh Jadav

Prodigy 40 points

Hello Brijesh,

Yes the instance I use under MCU2_0 are disabled in DT.

I have following config in pinmux:

static pinmuxPerCfg_t gI2c1PinCfg[] =
{
/* MyI2C1 -> I2C1_SCL -> AE34 */
{
PIN_MCASP0_AXR15, PIN_MODE(13) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
/* MyI2C1 -> I2C1_SDA -> AJ32 */
{
PIN_EXT_REFCLK1, PIN_MODE(13) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
{PINMUX_END}
};

static pinmuxPerCfg_t gI2c2PinCfg[] =
{
/* MyI2C2 -> I2C2_SCL -> AC32 */
{
PIN_MCASP1_AXR1, PIN_MODE(13) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
/* MyI2C2 -> I2C2_SDA -> AC37 */
{
PIN_MCASP1_AXR2, PIN_MODE(13) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
{PINMUX_END}
};

static pinmuxPerCfg_t gI2c3PinCfg[] =
{
/* MyI2C3 -> I2C3_SCL -> AF38 */
{
PIN_MCAN0_TX, PIN_MODE(13) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
/* MyI2C3 -> I2C3_SDA -> AA32 */
{
PIN_MMC1_DAT2, PIN_MODE(10) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
{PINMUX_END}
};

static pinmuxPerCfg_t gI2c4PinCfg[] =
{
/* MyI2C4 -> I2C4_SCL -> AG38 */
{
PIN_MCASP0_AXR5, PIN_MODE(13) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
/* MyI2C4 -> I2C4_SDA -> AK34 */
{
PIN_MCASP0_AXR4, PIN_MODE(13) | \
((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
},
{PINMUX_END}
};

I use I2C base addr:

#define CSL_I2C1_CFG_BASE (0x2010000UL)
#define CSL_I2C2_CFG_BASE (0x2020000UL)
#define CSL_I2C3_CFG_BASE (0x2030000UL)
#define CSL_I2C4_CFG_BASE (0x2040000UL

Are above settings correct?:

What do you mean by "power it on"?

0 Brijesh Jadav over 1 year ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Hi,

are you able to access I2C3 register? Can you please accessing them from CCS? If they are not accessible, I2C instance might not be powered on and it would need to be powered on explicitly.

Regards,

Brijesh

0 Wojciech Godek over 1 year ago in reply to Brijesh Jadav

Prodigy 40 points

Hello Brijesh,

Unfortunately I2C still is not working (tried from MCU2_0 and MCU3_0).

I got following trace from I2C driver:

I2C:(0x2010000) Starting transaction to slave: 0x50
Failing while transmitting the rd reg addr with error code - -3

I2C:(0x2020000) Starting transaction to slave: 0x50
Failing while transmitting the rd reg addr with error code - -1

Following pinmux config is used:

I can't use jtag due to the issue:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1392596/tda4vh-q1-ccs-problem-while-initialisation-j784s4_tda4vh

0 Brijesh Jadav over 1 year ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Hi WG,

Which exactly API is returning the error? and what exactly the parameter to this API?

Even if the pinmux is incorrect, driver should not error, in this case, you might not see correct i2c transaction.

Also if it is not powered on, register will not be accessible and so it might cause the crash, but should not return error.

So the issue is something else.. May be some parameter passed is incorrect or something else.

Regards,

Brijesh

0 Wojciech Godek over 1 year ago in reply to Brijesh Jadav

Prodigy 40 points

Hi Brijesh,

Below are two cases with I2C read operation for two different units (1&2)

1. I2C read for unit 1 base_addr=0x2020000

I2C_open_v1(base_addr=0x2020000, operMode=POOLING,bitRate=I2C_400kHz)

I2C_v1_waitForPin(I2C_INT_ADRR_READY_ACESS, timeout=2000)<---this fct returns timeout val =0
I2C_primeTransfer_v1(I2C_CFG_7BIT_SLAVE_ADDR,)
I2C_transfer_v1(MasterMode=1, OperationMode=POOLING, WriteCnt=2) -->this function returns code -3(timeout) or -1 (NACK)
I2C_transfer(); -->this function returns code -3(timeout) or -1 (NACK)
Board_i2c16BitRegRd(i2cAddr=0x50, regAddr=0x00D ,cnt=1,BOARD_I2C_REG_ADDR_MSB_FIRST,i2cTimeout=2000)

2. I2C read for unit 1 base_addr=0x2010000
I2C_open_v1(base_addr=0x2010000, operMode=POOLING,bitRate=I2C_400kHz)

I2CMasterIntRawStatusEx()<---this fct returns errStat=0x2(I2C_STS_ERR_NO_ACK)
I2C_primeTransfer_v1(I2C_CFG_7BIT_SLAVE_ADDR)
I2C_transfer_v1(MasterMode=1, OperationMode=POOLING, WriteCnt=2) -->this function returns code -3(timeout) or -1 (NACK)
I2C_transfer(); -->this function returns code -3(timeout) or -1 (NACK)
Board_i2c16BitRegRd(i2cAddr=0x50, regAddr=0x00D ,cnt=1,BOARD_I2C_REG_ADDR_MSB_FIRST,i2cTimeout=2000)

Both above cases returns error. What could be the reason?

Best Regards

Wojciech

0 Brijesh Jadav over 1 year ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Hi WG,

Are you sure that the I2C is disabled for both of these instances on A72 or other cores and you are using it only from R5F code? Also are you seeing this error on the first i2c transaction?

Can you also check the value of the pinmux register for both the i2c pins and confirm that they are correct, where the error happens?

Regards,

Brijesh

0 Wojciech Godek over 1 year ago in reply to Brijesh Jadav

Prodigy 40 points

Hi Brijesh,

Yes I have disabled all I2C instances in DT. I am using only one core R5.

I changed the HW and now can see a trace but driver still shows the error.

Please see attached picture

0 Wojciech Godek over 1 year ago in reply to Wojciech Godek

Prodigy 40 points

What could be the reason that driver returns error?

0 Brijesh Jadav over 1 year ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Hi WG,

Not exactly sure, do you happen to have JTAG + CCS connected on this board? Can you please go inside this API to know where it exactly returns error?

Regards,

Brijesh

0 Wojciech Godek 11 months ago in reply to Brijesh Jadav

Prodigy 40 points

Hi Brijesh,

I2C is now working, but still can't see CSI clock as output from uP. I use CSI/DMA settings from example camera_capture_test.

Tried first on MCU2/CSI1.
Could you please guide me what can be checked to diagnose the issue?

Wojciech

0 Brijesh Jadav 11 months ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Wojciech,

I can help from CSIRX perspective, but i am not sure why the sensor is not outputting data even if it is configured.. Could you please check with your sensor vendor?

Regards,

Brijesh

0 Wojciech Godek 11 months ago in reply to Brijesh Jadav

Prodigy 40 points

Hi Brijesh,

I prepared camera with image stream 1120x1360.
With following settings I have ECC error reported by driver (CSIRX_INSTANCE_ID_0):

/**< Number of CSIRX instances exist in SOC */
#define APP_TOTAL_CAPT_INST (CSIRX_INSTANCE_ID_MAX)
/**< Number of CSIRX instances to test parallelly */
#define APP_CAPT_TEST_INST_NUM ((uint32_t)1U)
/**< Number of channels */
#define APP_CAPT_CH_NUM ((uint32_t)1U)
/**< Input Image Data format */
#define APP_CAPT_IMAGE_DT (FVID2_CSI2_DF_RAW8)
/**< Frame storage format. Only valid for RAW12 DT. */
#define APP_CAPT_IMAGE_STORAGE_FORMAT FVID2_CCSF_BITS8_PACKED
/**< Number of frames per stream */
#define APP_CAPT_FRAMES_PER_CH ((uint32_t)1U)
/**< Frame Attribute: Width in pixels */
#define APP_CAPT_FRAME_WIDTH ((uint32_t)1120U)
/**< Frame Attribute: Height in pixels */
#define APP_CAPT_FRAME_HEIGHT ((uint32_t)1360U)
/**< Frame Attribute: Bytes per pixel */
#define APP_CAPT_FRAME_BPP ((uint32_t)1U) /*when set to 1 it causes crash*/

/**< I2C transaction timeout */
#define APP_I2C_TRANSACTION_TIMEOUT ((uint32_t)2000U)

/**< Time period to receive frames in app */
#define APP_TEST_PERIOD_IN_SEC ((uint32_t)10)

Frames Received: 0
Frames Received with errors: 0
Capture Application Completed!!!
FIFO Overflow Count: 0
Spurious UDMA interrupt count: 0
Front FIFO Overflow Count: 0
CRC Error Count: 0
Un-corrected ECC Error Count: 274822427
Corrected ECC Error Count: 0
Data ID Error Count: 0
Invalid Access Error Count: 0
Invalid Short Packet Receive Error Count: 0
Stream0 FIFO Overflow Error Count: 0
Stream1 FIFO Overflow Error Count: 0
Channel No: 0] | Frame Queue Count: 1 | Frame De-queue Count: 0 | Frame Drop Count: 0
0 frames captured in 10000 msec at the rate of 0. 0 frames/sec.

Please find attached startup logs.

What else setting can be connected to the error?

Fullscreen R53_0_udma_main.txt Download

0001: [AP]  <2024-09-30> <12:24:31.805> Camera_CaptureInit ... !!!
0002: [AP]  <2024-09-30> <12:24:31.821> : UdmaInitPrms_init(instId 2)
0003: [AP]  <2024-09-30> <12:24:31.867>  I2C InitCfg start: i2cCfg->baseAddr[0]:40b00000 (h:a2687e34)
0004: [AP]  <2024-09-30> <12:24:31.929> : init I2C base addr 0/40b00000 
0005: [AP]  <2024-09-30> <12:24:31.964> : i2cCfg->baseAddr[1]:40b10000 (h:a2687e34)
0006: [AP]  <2024-09-30> <12:24:32.008> : init I2C base addr 1/40b10000 
0007: [AP]  <2024-09-30> <12:24:32.053> : i2cCfg->baseAddr[2]:0 (h:a2687e34)
0008: [AP]  <2024-09-30> <12:24:32.084> : init I2C base addr 2/0 
0009: [AP]  <2024-09-30> <12:24:32.115> : i2cCfg->baseAddr[3]:0 (h:a2687e34)
0010: [AP]  <2024-09-30> <12:24:32.161> : init I2C base addr 3/0 
0011: [AP]  <2024-09-30> <12:24:32.178> : i2cCfg->baseAddr[4]:0 (h:a2687e34)
0012: [AP]  <2024-09-30> <12:24:32.224> : init I2C base addr 4/0 
0013: [AP]  <2024-09-30> <12:24:32.255> : i2cCfg->baseAddr[5]:0 (h:a2687e34)
0014: [AP]  <2024-09-30> <12:24:32.301> : init I2C base addr 5/0 
0015: [AP]  <2024-09-30> <12:24:32.317> : i2cCfg->baseAddr[6]:0 (h:a2687e34)
0016: [AP]  <2024-09-30> <12:24:32.364> : init I2C base addr 6/0 
0024: [AP]  <2024-09-30> <12:24:32.719>  InitCfg end: Sample Application - STARTS !!!
0025: [AP]  <2024-09-30> <12:24:32.767> :===================Setup Details===================
0026: [AP]  <2024-09-30> <12:24:32.828> : Capture Instance: 0
0027: [AP]  <2024-09-30> <12:24:32.843> : Capture DF:0x2a
0028: [AP]  <2024-09-30> <12:24:32.874> : Capture Resolution:1120 x 1360
0029: [AP]  <2024-09-30> <12:24:32.906> :===================================================
0030: [AP]  <2024-09-30> <12:24:32.952> CsirxDrv_create:0,0
0031: [AP]  <2024-09-30> <12:24:32.983> src/csirx_drv.c @ Line 334: start cfg chan0
0032: [AP]  <2024-09-30> <12:24:33.031> src/csirx_drv.c @ Line 340: CsirxDrv_setChCfgParams 0
0033: [AP]  <2024-09-30> <12:24:33.078> [UDMA] [Info]Udma_chAllocResource ChT 12
0034: [AP]  <2024-09-30> <12:24:33.123> [UDMA] [Info] Alloc result 0
0035: [AP]  <2024-09-30> <12:24:33.154> [UDMA] [Info] chHandle->fqRing A2576C80, instT 1 ret 0
0036: [AP]  <2024-09-30> <12:24:33.215> [UDMA] [Info] Alloc result 0,ringMem a2610d00
0037: [AP]  <2024-09-30> <12:24:33.261> [UDMA] [Info] chHandle->cqRing A2576C80, instT 1
0038: [AP]  <2024-09-30> <12:24:33.309> src/csirx_drv.c @ Line 347: CsirxDrv_setChUdmaParams 0
0039: [AP]  <2024-09-30> <12:24:33.370> src/csirx_drv.c @ Line 354: CsirxDrv_createChQueues 0
0040: [AP]  <2024-09-30> <12:24:33.418> src/csirx_drv.c @ Line 360: CsirxDrv_chConfigShim 0
0041: [AP]  <2024-09-30> <12:24:33.463> src/csirx_drv.c @ Line 385: CsirxDrv_setCslCfgParams 0
0042: [AP]  <2024-09-30> <12:24:33.525> :Set D-PHY Configuration Successful for CSIRX instance 0!!!
0043: [AP]  <2024-09-30> <12:24:33.587> Events Registration Successful for CSIRX instance 0!!!
0044: [AP]  <2024-09-30> <12:24:33.649> I2C 1 obj_inst:0 Open baseAddr:2010000
0045: [AP]  <2024-09-30> <12:24:33.695> I2C 28 Open OK ret 0, h a265e09c
0046: [AP]  <2024-09-30> <12:24:33.729> : CSIRX Capture created for CSIRX instance 0
0047: [AP]  <2024-09-30> <12:24:33.773> powerSet a263fab8/a263fab8/a2678594
0048: [AP]  <2024-09-30> <12:24:33.820> powerSet a263fab8/a2678594
0049: [AP]  <2024-09-30> <12:24:33.851> powerSet2 a263fab8/a2678594
0050: [AP]  <2024-09-30> <12:24:33.882> imagerApplyStartupPatch addr a262d3cc
0051: [AP]  <2024-09-30> <12:24:34.921> ->TracePoints:0;drvObj->deserApi->powerSet: a263fab8
0100: [AP]  <2024-09-30> <12:25:00.920> : ProcessTimerIsr
0101: [AP]  <2024-09-30> <12:25:00.921> :After stream end
0102: [AP]  <2024-09-30> <12:25:00.936> : CPU Load is:4 percent
0103: [AP]  <2024-09-30> <12:25:00.951> : Task Load is: 3 percent
0104: [AP]  <2024-09-30> <12:25:00.983> ==========================================================
0105: [AP]  <2024-09-30> <12:25:01.029> : Capture Status:
0106: [AP]  <2024-09-30> <12:25:01.059> : Capture instance:0
0107: [AP]  <2024-09-30> <12:25:01.076> ==========================================================
0108: [AP]  <2024-09-30> <12:25:01.137> : Frames Received: 0
0109: [AP]  <2024-09-30> <12:25:01.153> : Frames Received with errors: 0
0110: [AP]  <2024-09-30> <12:25:01.184> : Capture Application Completed!!!
0111: [AP]  <2024-09-30> <12:25:01.216> : FIFO Overflow Count: 0
0112: [AP]  <2024-09-30> <12:25:01.245> : Spurious UDMA interrupt count: 0
0113: [AP]  <2024-09-30> <12:25:01.276> : Front FIFO Overflow Count: 0
0114: [AP]  <2024-09-30> <12:25:01.307> : CRC Error Count: 0
0115: [AP]  <2024-09-30> <12:25:01.323> : Un-corrected ECC Error Count: 729323
0116: [AP]  <2024-09-30> <12:25:01.354> : Corrected ECC Error Count: 0
0117: [AP]  <2024-09-30> <12:25:01.386> : Data ID Error Count: 0
0118: [AP]  <2024-09-30> <12:25:01.416> : Invalid Access Error Count: 0
0119: [AP]  <2024-09-30> <12:25:01.432> : Invalid Short Packet Receive Error Count: 0
0120: [AP]  <2024-09-30> <12:25:01.478> : Stream0 FIFO Overflow Error Count: 0
0121: [AP]  <2024-09-30> <12:25:01.510> : Stream1 FIFO Overflow Error Count: 0
0122: [AP]  <2024-09-30> <12:25:01.541> :[Channel No: 0] | Frame Queue Count: 1 | Frame De-queue Count: 0 | Frame Drop Count: 0 
0123: [AP]  <2024-09-30> <12:25:01.632> : 0 frames captured in 10000 msec at the rate of 0. 0 frames/sec.
0151: [AP]  <2024-09-30> <12:25:10.973> : ProcessTimerIsr
0152: [AP]  <2024-09-30> <12:25:10.989> :After stream end
0153: [AP]  <2024-09-30> <12:25:11.004> : CPU Load is:3 percent
0154: [AP]  <2024-09-30> <12:25:11.020> : Task Load is: 2 percent
0155: [AP]  <2024-09-30> <12:25:11.052> ==========================================================
0156: [AP]  <2024-09-30> <12:25:11.113> : Capture Status:
0157: [AP]  <2024-09-30> <12:25:11.129> : Capture instance:0
0158: [AP]  <2024-09-30> <12:25:11.144> ==========================================================
0159: [AP]  <2024-09-30> <12:25:11.191> : Frames Received: 0
0160: [AP]  <2024-09-30> <12:25:11.221> : Frames Received with errors: 0
0161: [AP]  <2024-09-30> <12:25:11.252> : Capture Application Completed!!!
0162: [AP]  <2024-09-30> <12:25:11.283> : FIFO Overflow Count: 0
0163: [AP]  <2024-09-30> <12:25:11.300> : Spurious UDMA interrupt count: 0
0164: [AP]  <2024-09-30> <12:25:11.331> : Front FIFO Overflow Count: 0
0165: [AP]  <2024-09-30> <12:25:11.362> : CRC Error Count: 0
0166: [AP]  <2024-09-30> <12:25:11.377> : Un-corrected ECC Error Count: 1552624
0167: [AP]  <2024-09-30> <12:25:11.408> : Corrected ECC Error Count: 0
0168: [AP]  <2024-09-30> <12:25:11.439> : Data ID Error Count: 0
0169: [AP]  <2024-09-30> <12:25:11.470> : Invalid Access Error Count: 0
0170: [AP]  <2024-09-30> <12:25:11.500> : Invalid Short Packet Receive Error Count: 0
0171: [AP]  <2024-09-30> <12:25:11.533> : Stream0 FIFO Overflow Error Count: 0
0172: [AP]  <2024-09-30> <12:25:11.577> : Stream1 FIFO Overflow Error Count: 0
0173: [AP]  <2024-09-30> <12:25:11.609> :[Channel No: 0] | Frame Queue Count: 1 | Frame De-queue Count: 0 | Frame Drop Count: 0 
0174: [AP]  <2024-09-30> <12:25:11.687> : 0 frames captured in 10000 msec at the rate of 0. 0 frames/sec.

Wojciech

0 Brijesh Jadav 11 months ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Hi Wojciech,

There are a lot of ECC uncorrectable error reported by CSIRX. Is the CSIRX lane speed matching with the output lane speed of sensor/deserialzier? Also are the number of lanes configured in the CSIRX matching with the output of deserializer and connected in HW?

Regards,

Brijesh

0 Wojciech Godek 11 months ago in reply to Brijesh Jadav

Prodigy 40 points

Hi Brijesh,

Where can I find the parameter settings you mentioned?

Best Regards

Wojciech

0 Brijesh Jadav 11 months ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Hi,

not sure from sensor/deserializer side, but from csirx, lane band speed parameters is used.

Regards,

Brijesh

0 Wojciech Godek 11 months ago in reply to Brijesh Jadav

Prodigy 40 points

Hi,

Yes, My question is only about configuration from CSIRX component side.

As I mentioned before my application on MCU2 is besed on sample app from

pdk_j784s4_09_02_00_30\packages\ti\drv\csirx\examples\csirx_capture_test.

Is there any description how to adjust configuration?

On my board MIPI speed is set to 900Mbps/Msps.

I attached the file with my current settings.

How to adjust the setting for the given speed?

Anything else has to be checked?

Fullscreen camera_settings_capture_test.txt Download

/**< Frame Attribute: Pitch in bytes */
#define APP_CAPT_FRAME_PITCH                      ((uint32_t)\
                                (APP_CAPT_FRAME_WIDTH * APP_CAPT_FRAME_BPP))
/**< Frame Attribute: size in bytes */
#define APP_CAPT_FRAME_SIZE                                ((uint32_t)\
            (APP_CAPT_FRAME_HEIGHT * APP_CAPT_FRAME_WIDTH * APP_CAPT_FRAME_BPP))

/**< For Ub960 Pattern Generator, most significant byte of active line length in
 * bytes 
 */
#define APP_CAPT_FRAME_LINE_LEN_HIGH           ((APP_CAPT_FRAME_PITCH & 0xFF00)>>8)



/**< Number of CSIRX instances exist in SOC */
#define APP_TOTAL_CAPT_INST                       (CSIRX_INSTANCE_ID_MAX)
/**< Number of CSIRX instances to test parallelly */
#define APP_CAPT_TEST_INST_NUM                    ((uint32_t)1U)
/**< Number of channels */
#define APP_CAPT_CH_NUM                           ((uint32_t)1U)//4
/**< Input Image Data format */
#define APP_CAPT_IMAGE_DT                         (FVID2_CSI2_DF_RAW8)//FVID2_CCSF_BITS12_UNPACKED16
/**< Frame storage format. Only valid for RAW12 DT. */
#define APP_CAPT_IMAGE_STORAGE_FORMAT             FVID2_CCSF_BITS8_PACKED//(FVID2_CCSF_BITS12_UNPACKED16)
/**< Number of frames per stream */
#define APP_CAPT_FRAMES_PER_CH                    ((uint32_t)4U)//WGO  orginally was 4
/**< Frame Attribute: Width in pixels */
#define APP_CAPT_FRAME_WIDTH                      ((uint32_t)1120U)
/**< Frame Attribute: Height in pixels */
#define APP_CAPT_FRAME_HEIGHT                     ((uint32_t)1360U)
/**< Frame Attribute: Bytes per pixel */
#define APP_CAPT_FRAME_BPP                        ((uint32_t)1U)        /*when set to 1 it causes crash*/

/**< I2C transaction timeout */
#define APP_I2C_TRANSACTION_TIMEOUT               ((uint32_t)2000U)



static void CameraApp_initCaptParams(CsirxApp_CaptInstObj* appInstObj)
{
    uint32_t loopCnt = 0U;

    if (CSIRX_INSTANCE_ID_0 == appInstObj->instId)
    {
        appInstObj->boardCsiInstID = BOARD_CSI_INST_0;//WGO CEER
        appInstObj->cameraSensor = APP_CSIRX_INST0_CAMERA_SENSOR;
    }
    else if (CSIRX_INSTANCE_ID_1 == appInstObj->instId)
    {
        appInstObj->boardCsiInstID = BOARD_CSI_INST_1;
        appInstObj->cameraSensor = APP_CSIRX_INST1_CAMERA_SENSOR;
    }
#if defined(SOC_J784S4)
    else if (CSIRX_INSTANCE_ID_2 == appInstObj->instId)
    {
        appInstObj->boardCsiInstID = BOARD_CSI_INST_2;
        appInstObj->cameraSensor = APP_CSIRX_INST2_CAMERA_SENSOR;
    }
#endif
    else
    {
        GT_0trace(CsirxAppTrace, GT_ERR,
                  APP_NAME ": Invalid Capture Instance\r\n");
    }

    /* set instance configuration parameters */
    Csirx_createParamsInit(&appInstObj->createPrms);
    appInstObj->createPrms.numCh = APP_CAPT_CH_NUM;
    /* set channel configuration parameters */
    for (loopCnt = 0U ; loopCnt < appInstObj->createPrms.numCh ; loopCnt++)
    {
        appInstObj->chFrmCnt[loopCnt] = 0U;
        appInstObj->createPrms.chCfg[loopCnt].chId = loopCnt;
        appInstObj->createPrms.chCfg[loopCnt].chType = CSIRX_CH_TYPE_CAPT;
        appInstObj->createPrms.chCfg[loopCnt].vcNum = loopCnt;
        appInstObj->createPrms.chCfg[loopCnt].inCsiDataType = APP_CAPT_IMAGE_DT;
        appInstObj->createPrms.chCfg[loopCnt].outFmt.width = APP_CAPT_FRAME_WIDTH;
        appInstObj->createPrms.chCfg[loopCnt].outFmt.height = APP_CAPT_FRAME_HEIGHT;
        appInstObj->createPrms.chCfg[loopCnt].outFmt.pitch[0U] =
                                                APP_CAPT_FRAME_PITCH;
        appInstObj->createPrms.chCfg[loopCnt].outFmt.dataFormat =
                                                FVID2_DF_BGRX32_8888;
        appInstObj->createPrms.chCfg[loopCnt].outFmt.ccsFormat =
                                                APP_CAPT_IMAGE_STORAGE_FORMAT;
    }
    /* set module configuration parameters */
    appInstObj->createPrms.instCfg.enableCsiv2p0Support = UTRUE;
    appInstObj->createPrms.instCfg.numDataLanes = 4U;
    appInstObj->createPrms.instCfg.enableErrbypass = UTRUE;//  WGO changed from UFALSE;
    appInstObj->createPrms.instCfg.enableStrm[CSIRX_CAPT_STREAM_ID] = 1U;
    for (loopCnt = 0U ;
         loopCnt < appInstObj->createPrms.instCfg.numDataLanes ;
         loopCnt++)
    {
        appInstObj->createPrms.instCfg.dataLanesMap[loopCnt] = (loopCnt + 1U);
    }
    /* set frame drop buffer parameters */
    appInstObj->createPrms.frameDropBufLen =
                                (APP_CAPT_FRAME_WIDTH * APP_CAPT_FRAME_BPP);
    appInstObj->createPrms.frameDropBuf = (uint64_t)&gFrmDropBuf;
    /* This will be updated once Fvid2_create() is done */
    appInstObj->createStatus.retVal = FVID2_SOK;
    appInstObj->drvHandle = NULL;
    Fvid2CbParams_init(&appInstObj->cbPrms);
    appInstObj->cbPrms.cbFxn   = (Fvid2_CbFxn) &CsirxApp_frameCompletionCb;
    appInstObj->cbPrms.appData = appInstObj;

    appInstObj->numFramesRcvd = 0U;
    appInstObj->frameErrorCnt = 0U;
    appInstObj->maxWidth = APP_CAPT_FRAME_WIDTH;
    appInstObj->maxHeight = APP_CAPT_FRAME_HEIGHT;

    /* Initialize capture instance status */
    Csirx_instStatusInit(&appInstObj->captStatus);
}

0 Brijesh Jadav 11 months ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Hi WG,

This example uses default lane band speed, ie 1.35 to 1.5Gbps. You would have to overwrite lane speed. Below code uses default lane band speed.

/* Set CSIRX D-PHY configuration parameters */
Csirx_initDPhyCfg(&dphyCfg);
dphyCfg.inst = appInstObj->instId;
retVal = Fvid2_control(appInstObj->drvHandle,
IOCTL_CSIRX_SET_DPHY_CONFIG,
&dphyCfg,
NULL);

After calling Csirx_initDPhyCfg API, you can overwrite dphyCfg->leftLaneBandSpeed and dphyCfg->rightLaneBandSpeed parameters to required lane speed. Can you please try changing it?

Regards,

Brijesh

0 Wojciech Godek 11 months ago in reply to Brijesh Jadav

Prodigy 40 points

Hi,

yes I use CSIRX_LANE_BAND_SPEED_880_TO_1040_MBPS because my MIPI speed is set to 900MBPS.

The ECC errors are still present means I don't see any frame received.

0 Brijesh Jadav 11 months ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Hi WG,

Can you please try few more lane speed around this lane speed?

Are you also seeing CRC errors? or just ECC errors?

is there any possibility of interference on the CSI lines?

Regards,

Brijesh

0 Wojciech Godek 10 months ago in reply to Brijesh Jadav

Prodigy 40 points

Hi Brijesh,

I changed the mapping of the MIPI lines on Deserilizer side. Now I can see frames reception is active but errors are detected.

in the test

Fvid2_control(IOCTL_CSITX_PRINT_DEBUG_LOGS)

Fvid2_control(IOCTL_CSITX_GET_INST_STATUS)

are called periodically.

but can see an error like this:

Frames Received with errors: 1983

Please find attached traces

What could be the reson for the error?

Best Regards

Fullscreen csi_capture_logs.log Download

serIF0-> <2024-10-09> <12:34:48.278> : UdmaInitPrms_init(instId 2)
serIF0-> <2024-10-09> <12:34:48.309>  I2C InitCfg start: i2cCfg->baseAddr[0]:40b00000 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:48.371> : init I2C base addr 0/40b00000 
serIF0-> <2024-10-09> <12:34:48.417> : i2cCfg->baseAddr[1]:40b10000 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:48.464> : init I2C base addr 1/40b10000 
serIF0-> <2024-10-09> <12:34:48.495> : i2cCfg->baseAddr[2]:0 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:48.541> : init I2C base addr 2/0 
serIF0-> <2024-10-09> <12:34:48.572> : i2cCfg->baseAddr[3]:0 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:48.604> : init I2C base addr 3/0 
serIF0-> <2024-10-09> <12:34:48.634> : i2cCfg->baseAddr[4]:0 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:48.681> : init I2C base addr 4/0 
serIF0-> <2024-10-09> <12:34:48.697> : i2cCfg->baseAddr[5]:0 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:48.743> : init I2C base addr 5/0 
serIF0-> <2024-10-09> <12:34:48.774> : i2cCfg->baseAddr[6]:0 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:48.805> : init I2C base addr 6/0 
serIF0-> <2024-10-09> <12:34:48.836> : i2cCfg->baseAddr[0]:2000000 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:48.884> : i2cCfg->baseAddr[1]:2010000 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:48.929> : i2cCfg->baseAddr[2]:2020000 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:48.975> : i2cCfg->baseAddr[3]:2030000 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:49.022> : i2cCfg->baseAddr[4]:2040000 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:49.069> : i2cCfg->baseAddr[5]:2050000 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:49.115> : i2cCfg->baseAddr[6]:2060000 (h:a298fe34)
serIF0-> <2024-10-09> <12:34:49.162>  InitCfg end: Sample Application - STARTS !!!
serIF0-> <2024-10-09> <12:34:49.208> :===================Setup Details===================
serIF0-> <2024-10-09> <12:34:49.270> : Capture Instance: 0
serIF0-> <2024-10-09> <12:34:49.301> : Capture DF:0x2a
serIF0-> <2024-10-09> <12:34:49.317> : Capture Resolution:1008 x 1300
serIF0-> <2024-10-09> <12:34:49.347> :===================================================
serIF0-> <2024-10-09> <12:34:49.412> CsirxDrv_create:0,0
serIF0-> <2024-10-09> <12:34:49.425> src/csirx_drv.c @ Line 334: start cfg chan0
serIF0-> <2024-10-09> <12:34:49.472> src/csirx_drv.c @ Line 340: CsirxDrv_setChCfgParams 0
serIF0-> <2024-10-09> <12:34:49.534> [UDMA] [Info]Udma_chAllocResource ChT 12
serIF0-> <2024-10-09> <12:34:49.580> [UDMA] [Info] Alloc result 0
serIF0-> <2024-10-09> <12:34:49.596> [UDMA] [Info] chHandle->fqRing A289AC80, instT 1 ret 0
serIF0-> <2024-10-09> <12:34:49.658> [UDMA] [Info] Alloc result 0,ringMem a2923680
serIF0-> <2024-10-09> <12:34:49.704> [UDMA] [Info] chHandle->cqRing A289AC80, instT 1
serIF0-> <2024-10-09> <12:34:49.751> src/csirx_drv.c @ Line 347: CsirxDrv_setChUdmaParams 0
serIF0-> <2024-10-09> <12:34:49.813> src/csirx_drv.c @ Line 354: CsirxDrv_createChQueues 0
serIF0-> <2024-10-09> <12:34:49.874> src/csirx_drv.c @ Line 360: CsirxDrv_chConfigShim 0
serIF0-> <2024-10-09> <12:34:49.921> src/csirx_drv.c @ Line 385: CsirxDrv_setCslCfgParams 0
serIF0-> <2024-10-09> <12:34:49.983> :Set D-PHY Configuration Successful for CSIRX instance 0!!!
serIF0-> <2024-10-09> <12:34:50.045> Events Registration Successful for CSIRX instance 0!!!
serIF0-> <2024-10-09> <12:34:50.092> I2C 1 obj_inst:0 Open baseAddr:2010000
serIF0-> <2024-10-09> <12:34:50.138> I2C 28 Open OK ret 0, h a296799c
serIF0-> <2024-10-09> <12:34:50.184> : CSIRX Capture created for CSIRX instance 0
serIF0-> <2024-10-09> <12:34:50.231> CameraDrv_Register a2950d70/a2981fb0
serIF0-> <2024-10-09> <12:34:50.262> imagerApplyStartupPatch addr a293e628TracePoints:01235/ 0/f=0
serIF0-> <2024-10-09> <12:34:50.339> drvObj->deserApi->powerSet: a2950d70
serIF0-> <2024-10-09> <12:34:54.895> :Before stream start
serIF0-> <2024-10-09> <12:34:54.911> : CPU Load is:16 percent
serIF0-> <2024-10-09> <12:34:54.943> : Task Load is: 15 percent
serIF0-> <2024-10-09> <12:34:54.973> src/csirx_drv.c @ Line 1435: CSIRX_DRV_STATE_RUNNING stream 1-0 
serIF0-> <2024-10-09> <12:35:05.387> TracePoints:01235/ 610/f=610
serIF0-> <2024-10-09> <12:35:05.419> :After stream end
serIF0-> <2024-10-09> <12:35:05.434> : CPU Load is:7 percent
serIF0-> <2024-10-09> <12:35:05.465> : Task Load is: 6 percent
serIF0-> <2024-10-09> <12:35:05.496> : Capture Stop Failed for instance 0 retVal -8!!!
serIF0-> <2024-10-09> <12:35:05.543> =====================================================
serIF0-> <2024-10-09> <12:35:05.605> ::Debug Logs::
serIF0-> <2024-10-09> <12:35:05.620> =====================================================
serIF0-> <2024-10-09> <12:35:05.682> [LOG]Frame: 0 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 17314 |
serIF0-> <2024-10-09> <12:35:05.775> [LOG]Frame: 1 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 17331 |
serIF0-> <2024-10-09> <12:35:05.868> [LOG]Frame: 2 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 17347 |
serIF0-> <2024-10-09> <12:35:05.977> [LOG]Frame: 3 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 17697 |
serIF0-> <2024-10-09> <12:35:06.070> [LOG]Frame: 4 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 17714 |
serIF0-> <2024-10-09> <12:35:06.178> [LOG]Frame: 5 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 17731 |
serIF0-> <2024-10-09> <12:35:06.272> [LOG]Frame: 6 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 17747 |
serIF0-> <2024-10-09> <12:35:06.379> [LOG]Frame: 7 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18097 |
serIF0-> <2024-10-09> <12:35:06.473> [LOG]Frame: 8 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18114 |
serIF0-> <2024-10-09> <12:35:06.580> [LOG]Frame: 9 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18130 |
serIF0-> <2024-10-09> <12:35:06.674> [LOG]Frame: 10 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18147 |
serIF0-> <2024-10-09> <12:35:06.782> [LOG]Frame: 11 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18497 |
serIF0-> <2024-10-09> <12:35:06.875> [LOG]Frame: 12 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18514 |
serIF0-> <2024-10-09> <12:35:06.983> [LOG]Frame: 13 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18530 |
serIF0-> <2024-10-09> <12:35:07.077> [LOG]Frame: 14 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18547 |
serIF0-> <2024-10-09> <12:35:07.185> [LOG]Frame: 15 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18897 |
serIF0-> <2024-10-09> <12:35:07.279> [LOG]Frame: 16 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18914 |
serIF0-> <2024-10-09> <12:35:07.387> [LOG]Frame: 17 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18930 |
serIF0-> <2024-10-09> <12:35:07.480> [LOG]Frame: 18 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 18947 |
serIF0-> <2024-10-09> <12:35:07.588> [LOG]Frame: 19 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 19297 |
serIF0-> <2024-10-09> <12:35:07.696> =====================================================
serIF0-> <2024-10-09> <12:35:07.744> ::TR Submit Debug Logs::
serIF0-> <2024-10-09> <12:35:07.775> =====================================================
serIF0-> <2024-10-09> <12:35:07.821> [LOG]TR Submit No.: 0 | CH ID: -1567814400 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:07.898> [LOG]TR Submit No.: 1 | CH ID: -1567814144 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:07.962> [LOG]TR Submit No.: 2 | CH ID: -1567813888 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.022> [LOG]TR Submit No.: 3 | CH ID: -1567813632 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.099> [LOG]TR Submit No.: 4 | CH ID: -1567813376 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.162> [LOG]TR Submit No.: 5 | CH ID: -1567813120 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.224> [LOG]TR Submit No.: 6 | CH ID: -1567812864 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.301> [LOG]TR Submit No.: 7 | CH ID: -1567812608 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.363> [LOG]TR Submit No.: 8 | CH ID: -1567812352 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.426> [LOG]TR Submit No.: 9 | CH ID: -1567812096 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.502> [LOG]TR Submit No.: 10 | CH ID: -1567814400 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.565> [LOG]TR Submit No.: 11 | CH ID: -1567814144 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.628> [LOG]TR Submit No.: 12 | CH ID: -1567813888 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.704> [LOG]TR Submit No.: 13 | CH ID: -1567813632 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.767> [LOG]TR Submit No.: 14 | CH ID: -1567813376 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.843> [LOG]TR Submit No.: 15 | CH ID: -1567813120 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.905> [LOG]TR Submit No.: 16 | CH ID: -1567812864 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:08.968> [LOG]TR Submit No.: 17 | CH ID: -1567812608 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.045> [LOG]TR Submit No.: 18 | CH ID: -1567812352 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.107> [LOG]TR Submit No.: 19 | CH ID: -1567812096 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.184> =====================================================
serIF0-> <2024-10-09> <12:35:09.231> ::TR Out/Complete Debug Logs::
serIF0-> <2024-10-09> <12:35:09.277> =====================================================
serIF0-> <2024-10-09> <12:35:09.324> [LOG]TR Out No.: 0 | CH ID: -1567814400 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.386> [LOG]TR Out No.: 1 | CH ID: -1567814144 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.463> [LOG]TR Out No.: 2 | CH ID: -1567813888 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.526> [LOG]TR Out No.: 3 | CH ID: -1567813632 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.587> [LOG]TR Out No.: 4 | CH ID: -1567813376 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.652> [LOG]TR Out No.: 5 | CH ID: -1567813120 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.712> [LOG]TR Out No.: 6 | CH ID: -1567812864 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.774> [LOG]TR Out No.: 7 | CH ID: -1567812608 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.851> [LOG]TR Out No.: 8 | CH ID: -1567812352 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.913> [LOG]TR Out No.: 9 | CH ID: -1567812096 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:09.975> [LOG]TR Out No.: 10 | CH ID: -1567814400 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:10.037> [LOG]TR Out No.: 11 | CH ID: -1567814144 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:10.114> [LOG]TR Out No.: 12 | CH ID: -1567813888 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:10.181> [LOG]TR Out No.: 13 | CH ID: -1567813632 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:10.238> [LOG]TR Out No.: 14 | CH ID: -1567813376 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:10.301> [LOG]TR Out No.: 15 | CH ID: -1567813120 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:10.378> [LOG]TR Out No.: 16 | CH ID: -1567812864 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:10.440> [LOG]TR Out No.: 17 | CH ID: -1567812608 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:10.502> [LOG]TR Out No.: 18 | CH ID: -1567812352 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:10.564> [LOG]TR Out No.: 19 | CH ID: -1567812096 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:10.641> =====================================================
serIF0-> <2024-10-09> <12:35:10.703> ::Event Debug Logs::
serIF0-> <2024-10-09> <12:35:10.722> =====================================================
serIF0-> <2024-10-09> <12:35:10.781> :Get Capture Status Failed!!!
serIF0-> <2024-10-09> <12:35:10.812> ==========================================================
serIF0-> <2024-10-09> <12:35:10.874> : Capture Status:
serIF0-> <2024-10-09> <12:35:10.889> : Capture instance:0
serIF0-> <2024-10-09> <12:35:10.921> ==========================================================
serIF0-> <2024-10-09> <12:35:10.986> : Frames Received: 946
serIF0-> <2024-10-09> <12:35:11.013> : Frames Received with errors: 948
serIF0-> <2024-10-09> <12:35:11.045> : Capture Application Completed!!!
serIF0-> <2024-10-09> <12:35:11.091> : FIFO Overflow Count: 0
serIF0-> <2024-10-09> <12:35:11.106> : Spurious UDMA interrupt count: 0
serIF0-> <2024-10-09> <12:35:11.153> : Front FIFO Overflow Count: 0
serIF0-> <2024-10-09> <12:35:11.184> : CRC Error Count: 0
serIF0-> <2024-10-09> <12:35:11.215> : Un-corrected ECC Error Count: 0
serIF0-> <2024-10-09> <12:35:11.246> : Corrected ECC Error Count: 0
serIF0-> <2024-10-09> <12:35:11.277> : Data ID Error Count: 0
serIF0-> <2024-10-09> <12:35:11.308> : Invalid Access Error Count: 0
serIF0-> <2024-10-09> <12:35:11.339> : Invalid Short Packet Receive Error Count: 0
serIF0-> <2024-10-09> <12:35:11.386> : Stream0 FIFO Overflow Error Count: 0
serIF0-> <2024-10-09> <12:35:11.432> : Stream1 FIFO Overflow Error Count: 0
serIF0-> <2024-10-09> <12:35:11.479> :[Channel No: 0] | Frame Queue Count: 936 | Frame De-queue Count: 934 | Frame Drop Count: 0 
serIF0-> <2024-10-09> <12:35:11.572> : Error Frames Info...
serIF0-> <2024-10-09> <12:35:11.602> :[Frame No.: 0] | Channel Id: 0 | Ch Error Frame Number: 981 | Time-stamp(ms): 23313 
serIF0-> <2024-10-09> <12:35:11.680> :[Frame No.: 1] | Channel Id: 0 | Ch Error Frame Number: 982 | Time-stamp(ms): 23330 
serIF0-> <2024-10-09> <12:35:11.773> :[Frame No.: 2] | Channel Id: 0 | Ch Error Frame Number: 993 | Time-stamp(ms): 23513 
serIF0-> <2024-10-09> <12:35:11.866> :[Frame No.: 3] | Channel Id: 0 | Ch Error Frame Number: 994 | Time-stamp(ms): 23530 
serIF0-> <2024-10-09> <12:35:11.958> :[Frame No.: 4] | Channel Id: 0 | Ch Error Frame Number: 995 | Time-stamp(ms): 23546 
serIF0-> <2024-10-09> <12:35:12.037> :[Frame No.: 5] | Channel Id: 0 | Ch Error Frame Number: 1006 | Time-stamp(ms): 23730 
serIF0-> <2024-10-09> <12:35:12.129> :[Frame No.: 6] | Channel Id: 0 | Ch Error Frame Number: 1007 | Time-stamp(ms): 23746 
serIF0-> <2024-10-09> <12:35:12.222> :[Frame No.: 7] | Channel Id: 0 | Ch Error Frame Number: 1018 | Time-stamp(ms): 23929 
serIF0-> <2024-10-09> <12:35:12.315> :[Frame No.: 8] | Channel Id: 0 | Ch Error Frame Number: 1019 | Time-stamp(ms): 23946 
serIF0-> <2024-10-09> <12:35:12.408> :[Frame No.: 9] | Channel Id: 0 | Ch Error Frame Number: 1030 | Time-stamp(ms): 24129 
serIF0-> <2024-10-09> <12:35:12.486> : 1037 frames captured in 10000 msec at the rate of 62. 0 frames/sec.
serIF0-> <2024-10-09> <12:35:22.653> :After stream end
serIF0-> <2024-10-09> <12:35:22.684> : CPU Load is:4 percent
serIF0-> <2024-10-09> <12:35:22.699> : Task Load is: 3 percent
serIF0-> <2024-10-09> <12:35:22.729> : Capture Stop Failed for instance 0 retVal -8!!!
serIF0-> <2024-10-09> <12:35:22.791> =====================================================
serIF0-> <2024-10-09> <12:35:22.853> ::Debug Logs::
serIF0-> <2024-10-09> <12:35:22.869> =====================================================
serIF0-> <2024-10-09> <12:35:22.916> [LOG]Frame: 0 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 34644 |
serIF0-> <2024-10-09> <12:35:23.024> [LOG]Frame: 1 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 34661 |
serIF0-> <2024-10-09> <12:35:23.117> [LOG]Frame: 2 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 34678 |
serIF0-> <2024-10-09> <12:35:23.225> [LOG]Frame: 3 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 34694 |
serIF0-> <2024-10-09> <12:35:23.318> [LOG]Frame: 4 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35044 |
serIF0-> <2024-10-09> <12:35:23.412> [LOG]Frame: 5 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35061 |
serIF0-> <2024-10-09> <12:35:23.521> [LOG]Frame: 6 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35078 |
serIF0-> <2024-10-09> <12:35:23.615> [LOG]Frame: 7 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35094 |
serIF0-> <2024-10-09> <12:35:23.722> [LOG]Frame: 8 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35444 |
serIF0-> <2024-10-09> <12:35:23.817> [LOG]Frame: 9 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35461 |
serIF0-> <2024-10-09> <12:35:23.923> [LOG]Frame: 10 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35477 |
serIF0-> <2024-10-09> <12:35:24.017> [LOG]Frame: 11 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35494 |
serIF0-> <2024-10-09> <12:35:24.125> [LOG]Frame: 12 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35844 |
serIF0-> <2024-10-09> <12:35:24.218> [LOG]Frame: 13 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35861 |
serIF0-> <2024-10-09> <12:35:24.326> [LOG]Frame: 14 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35877 |
serIF0-> <2024-10-09> <12:35:24.419> [LOG]Frame: 15 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 35894 |
serIF0-> <2024-10-09> <12:35:24.528> [LOG]Frame: 16 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 36244 |
serIF0-> <2024-10-09> <12:35:24.622> [LOG]Frame: 17 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 36261 |
serIF0-> <2024-10-09> <12:35:24.730> [LOG]Frame: 18 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 36277 |
serIF0-> <2024-10-09> <12:35:24.822> [LOG]Frame: 19 | Inst: 0 | Ch ID: 0x0 | FRM TYPE: 0 | FRM Status: 0xb | TR Resp: 0x0 | TS: 36294 |
serIF0-> <2024-10-09> <12:35:24.931> =====================================================
serIF0-> <2024-10-09> <12:35:24.994> ::TR Submit Debug Logs::
serIF0-> <2024-10-09> <12:35:25.023> =====================================================
serIF0-> <2024-10-09> <12:35:25.070> [LOG]TR Submit No.: 0 | CH ID: -1567814400 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.147> [LOG]TR Submit No.: 1 | CH ID: -1567814144 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.209> [LOG]TR Submit No.: 2 | CH ID: -1567813888 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.271> [LOG]TR Submit No.: 3 | CH ID: -1567813632 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.334> [LOG]TR Submit No.: 4 | CH ID: -1567813376 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.411> [LOG]TR Submit No.: 5 | CH ID: -1567813120 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.473> [LOG]TR Submit No.: 6 | CH ID: -1567812864 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.535> [LOG]TR Submit No.: 7 | CH ID: -1567812608 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.613> [LOG]TR Submit No.: 8 | CH ID: -1567812352 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.675> [LOG]TR Submit No.: 9 | CH ID: -1567812096 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.737> [LOG]TR Submit No.: 10 | CH ID: -1567814400 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.814> [LOG]TR Submit No.: 11 | CH ID: -1567814144 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.876> [LOG]TR Submit No.: 12 | CH ID: -1567813888 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:25.953> [LOG]TR Submit No.: 13 | CH ID: -1567813632 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.015> [LOG]TR Submit No.: 14 | CH ID: -1567813376 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.077> [LOG]TR Submit No.: 15 | CH ID: -1567813120 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.155> [LOG]TR Submit No.: 16 | CH ID: -1567812864 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.217> [LOG]TR Submit No.: 17 | CH ID: -1567812608 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.294> [LOG]TR Submit No.: 18 | CH ID: -1567812352 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.357> [LOG]TR Submit No.: 19 | CH ID: -1567812096 | TRPD: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.434> =====================================================
serIF0-> <2024-10-09> <12:35:26.480> ::TR Out/Complete Debug Logs::
serIF0-> <2024-10-09> <12:35:26.512> =====================================================
serIF0-> <2024-10-09> <12:35:26.573> [LOG]TR Out No.: 0 | CH ID: -1567814400 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.636> [LOG]TR Out No.: 1 | CH ID: -1567814144 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.698> [LOG]TR Out No.: 2 | CH ID: -1567813888 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.761> [LOG]TR Out No.: 3 | CH ID: -1567813632 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.837> [LOG]TR Out No.: 4 | CH ID: -1567813376 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.899> [LOG]TR Out No.: 5 | CH ID: -1567813120 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:26.963> [LOG]TR Out No.: 6 | CH ID: -1567812864 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.023> [LOG]TR Out No.: 7 | CH ID: -1567812608 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.086> [LOG]TR Out No.: 8 | CH ID: -1567812352 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.162> [LOG]TR Out No.: 9 | CH ID: -1567812096 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.224> [LOG]TR Out No.: 10 | CH ID: -1567814400 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.287> [LOG]TR Out No.: 11 | CH ID: -1567814144 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.349> [LOG]TR Out No.: 12 | CH ID: -1567813888 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.426> [LOG]TR Out No.: 13 | CH ID: -1567813632 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.489> [LOG]TR Out No.: 14 | CH ID: -1567813376 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.550> [LOG]TR Out No.: 15 | CH ID: -1567813120 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.616> [LOG]TR Out No.: 16 | CH ID: -1567812864 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.690> [LOG]TR Out No.: 17 | CH ID: -1567812608 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.752> [LOG]TR Out No.: 18 | CH ID: -1567812352 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.814> [LOG]TR Out No.: 19 | CH ID: -1567812096 | pDesc: 0x0 | TS: 0 |
serIF0-> <2024-10-09> <12:35:27.891> =====================================================
serIF0-> <2024-10-09> <12:35:27.938> ::Event Debug Logs::
serIF0-> <2024-10-09> <12:35:27.969> =====================================================
serIF0-> <2024-10-09> <12:35:28.016> :Get Capture Status Failed!!!
serIF0-> <2024-10-09> <12:35:28.062> ==========================================================
serIF0-> <2024-10-09> <12:35:28.125> : Capture Status:
serIF0-> <2024-10-09> <12:35:28.139> : Capture instance:0
serIF0-> <2024-10-09> <12:35:28.171> ==========================================================
serIF0-> <2024-10-09> <12:35:28.233> : Frames Received: 1981
serIF0-> <2024-10-09> <12:35:28.263> : Frames Received with errors: 1983
serIF0-> <2024-10-09> <12:35:28.295> : Capture Application Completed!!!
serIF0-> <2024-10-09> <12:35:28.326> : FIFO Overflow Count: 0
serIF0-> <2024-10-09> <12:35:28.356> : Spurious UDMA interrupt count: 0
serIF0-> <2024-10-09> <12:35:28.403> : Front FIFO Overflow Count: 0
serIF0-> <2024-10-09> <12:35:28.434> : CRC Error Count: 0
serIF0-> <2024-10-09> <12:35:28.450> : Un-corrected ECC Error Count: 0
serIF0-> <2024-10-09> <12:35:28.496> : Corrected ECC Error Count: 0
serIF0-> <2024-10-09> <12:35:28.527> : Data ID Error Count: 0
serIF0-> <2024-10-09> <12:35:28.558> : Invalid Access Error Count: 0
serIF0-> <2024-10-09> <12:35:28.590> : Invalid Short Packet Receive Error Count: 0
serIF0-> <2024-10-09> <12:35:28.636> : Stream0 FIFO Overflow Error Count: 0
serIF0-> <2024-10-09> <12:35:28.682> : Stream1 FIFO Overflow Error Count: 0
serIF0-> <2024-10-09> <12:35:28.728> :[Channel No: 0] | Frame Queue Count: 1971 | Frame De-queue Count: 1969 | Frame Drop Count: 0 
serIF0-> <2024-10-09> <12:35:28.822> : Error Frames Info...
serIF0-> <2024-10-09> <12:35:28.852> :[Frame No.: 0] | Channel Id: 0 | Ch Error Frame Number: 2011 | Time-stamp(ms): 40477 
serIF0-> <2024-10-09> <12:35:28.945> :[Frame No.: 1] | Channel Id: 0 | Ch Error Frame Number: 2022 | Time-stamp(ms): 40660 
serIF0-> <2024-10-09> <12:35:29.024> :[Frame No.: 2] | Channel Id: 0 | Ch Error Frame Number: 2023 | Time-stamp(ms): 40677 
serIF0-> <2024-10-09> <12:35:29.116> :[Frame No.: 3] | Channel Id: 0 | Ch Error Frame Number: 2034 | Time-stamp(ms): 40860 
serIF0-> <2024-10-09> <12:35:29.210> :[Frame No.: 4] | Channel Id: 0 | Ch Error Frame Number: 2035 | Time-stamp(ms): 40877 
serIF0-> <2024-10-09> <12:35:29.302> :[Frame No.: 5] | Channel Id: 0 | Ch Error Frame Number: 2036 | Time-stamp(ms): 40893 
serIF0-> <2024-10-09> <12:35:29.394> :[Frame No.: 6] | Channel Id: 0 | Ch Error Frame Number: 2047 | Time-stamp(ms): 41077 
serIF0-> <2024-10-09> <12:35:29.472> :[Frame No.: 7] | Channel Id: 0 | Ch Error Frame Number: 2048 | Time-stamp(ms): 41093 
serIF0-> <2024-10-09> <12:35:29.565> :[Frame No.: 8] | Channel Id: 0 | Ch Error Frame Number: 2059 | Time-stamp(ms): 41276 
serIF0-> <2024-10-09> <12:35:29.658> :[Frame No.: 9] | Channel Id: 0 | Ch Error Frame Number: 2060 | Time-stamp(ms): 41293 
serIF0-> <2024-10-09> <12:35:29.751> : 2072 frames captured in 10000 msec at the rate of 165.40 frames/sec.

+1 Brijesh Jadav 10 months ago in reply to Wojciech Godek

TI__Guru**** 475765 points

Hi WG,

I dont see any other error. No ECC, CRC, overflow errors. Also this error is reported for all the received frames, which means this frame size configured in the CSIRX is not matching with the input frame size. Please make sure that the size are exactly matching. Even a single pixel/line mismatch will reported this error.

Regards,

Brijesh

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TDA4VH-Q1: CSI initialisation is failing.