• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 98 subscribers
  • Views 414 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VH-Q1: GPIO Bank DMA Transfer to Ring/Circular Buffer

jars121
Intellectual 635 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Tool/software:

Hi all,

I have a similar need to this question.

I'm interfacing the TDA4VH to 2 ADCs, both of which provide a 16-bit parallel interface. I'd really like to avoid needing to use an FPGA, so am looking at whether I can route the parallel lines into 16-bit GPIO banks, and have the data written to a ring buffer via DMA. The DMA transfer would be triggered by the clock/shift pulse sent to the ADC. As the two ADCs will be synchronised, ideally the one clock output (to the two ADCs) can be configured as the DMA trigger for both 16-bit GPIO banks to transfer their data to separate ring buffers.

I'm reading through the seemingly relevant sections in the TRM but I can't seem to determine whether this is possible or not. Any clarification and/or section references would be greatly appreciated.

Assuming the above is possible, what sort of transfer frequency am I likely to achieve? I.e. if I use a 50MHz clock (to shift data out of the ADC and as the DMA trigger source) would this be achievable?

Thanks!

  • 0
    TI__Guru**** 478345 points

    Hi,

    I am sorry, i am not able to get it. How ADC triggers 16 GPIO input? how do you want to use DMA in this case? 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 635 points

    Hi Brijesh,

    The MCU provides a clock to the ADC. On the falling edge of the clock, the ADC puts 16 bits of data on the 16 parallel output lines. Rather than reading the 16 bits of data with software, I'd like to use DMA to move the 16 bits of data from the GPIO bank to a buffer. I would design the circuit such that the clock line to the ADC was also used as a trigger input for the DMA transfer. I would probably look at using an SPI interface to provide the clock (and just not use the MISO/MOSI lines).

  • 0 in reply to jars121
    TI__Guru**** 478345 points

    Hi,

    But SPI clock input cannot be used to trigger GPIO read. But you can use ADC clock output to connect to one more GPIO and this GPIO can be used to trigger DMA to read register. 

    But the question is, how much time data would be available? You would probably have to do experiments to figure out if time is sufficient and if not, you would require to stretch clock and keep this data in the same state for this clock period.  

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 635 points

    Thank you for clarifying.

    Just to be clear, the following configuration is possible:

    1. Route the ADC clock to a spare GPIO on the SoC.
    2. Setup a DMA transfer, triggered on this GPIO.
    3. Configure the DMA transfer to read a contiguous 16-bit GPIO bank into a ring buffer.

    In terms of throughput/frequency, I can adjust the ADC clock as required. Do you have an estimate as to how fast this 16-bit GPIO bank DMA transfer can function? I.e. if I use a 10MHz ADC clock, could the DMA trigger and transfer of the 16-bit GPIO bank be reliably performed in 100ns?

  • +1 in reply to jars121
    TI__Guru**** 478345 points

    Hi,

    Yes, the above configuration seems possible. but i cannot confirm the performance, because it depends on the other parameters like load on the system, DDR BW etc.. You would have to experiments in your environment and figure out what could be ADC clock. 

    Regards,

    Brijesh 

  • 0 in reply to Brijesh Jadav
    Intellectual 635 points

    Understood, thank you for your assistance Brijesh. I'll proceed with this design intent and test the throughput in due course.